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Я его гонял в режиме (Single)Simulation. Пример работает, прерывания идут, буфер DMA обновляется. Могу послать всю папку на email.
/*---------------------------------------------------------------*/
/* The example performs a 32 word DMA receive after configuring */
/* the interrupt controller, the sport, and the dma engine. */
/*---------------------------------------------------------------*/
#define IRQCTL_PAGE 1
#define IPR0 0x200
#define IPR1 0x201
#define IPR2 0x202
#define IPR3 0x203
#define UART_IOPAGE 0x5
#define UART_BASE 0x1400
#define UART_THR (0x1400-UART_BASE)
#define UART_RBR (0x1400-UART_BASE)
#define UART_DLL (0x1400-UART_BASE)
#define UART_IER (0x1401-UART_BASE)
#define UART_DLH (0x1401-UART_BASE)
#define UART_IIR (0x1402-UART_BASE)
#define UART_LCR (0x1403-UART_BASE)
#define UART_MCR (0x1404-UART_BASE)
#define UART_LSR (0x1405-UART_BASE)
#define UART_MSR (0x1406-UART_BASE)
#define UART_SCR (0x1407-UART_BASE)
#define UART_DMA_CURR_PTR_RX (0x1500-UART_BASE)
#define UART_DMA_CONFIG_RX (0x1501-UART_BASE)
#define UART_DMA_START_PG_RX (0x1502-UART_BASE)
#define UART_DMA_START_ADDR_RX (0x1503-UART_BASE)
#define UART_DMA_COUNT_RX (0x1504-UART_BASE)
#define UART_DMA_NEXT_DESCR_RX (0x1505-UART_BASE)
#define UART_DMA_DESCR_RDY_RX (0x1506-UART_BASE)
#define UART_DMA_IRQSTAT_RX (0x1507-UART_BASE)
#define UART_DMA_CURR_PTR_TX (0x1580-UART_BASE)
#define UART_DMA_CONFIG_TX (0x1581-UART_BASE)
#define UART_DMA_START_PG_TX (0x1582-UART_BASE)
#define UART_DMA_START_ADDR_TX (0x1583-UART_BASE)
#define UART_DMA_COUNT_TX (0x1584-UART_BASE)
#define UART_DMA_NEXT_DESCR_TX (0x1585-UART_BASE)
#define UART_DMA_DESCR_RDY_TX (0x1586-UART_BASE)
#define UART_DMA_IRQSTAT_TX (0x1587-UART_BASE)
#define UART_LCR_DLAB 0x80
#define UART_LCR_BRK 0x40
#define UART_LCR_SticyParity 0x20
#define UART_LCR_EPS 0x10
#define UART_LCR_PEN 0x08
#define UART_LCR_STOP 0x04
#define UART_LCR_WLS_8 0x03
#define UART_LCR_WLS_7 0x02
#define UART_LCR_WLS_6 0x01
#define UART_LCR_WLS_5 0x00
.GLOBAL _main;
.GLOBAL START;
.GLOBAL rcv_ddb;
/************************************************************/
/* DMA Descriptor and Input Buffer Allocation/Init */
/************************************************************/
.SECTION/data data1;
.var rcv_ddb[5] = 0,0,0,0,0; /* DMA Descriptor */
.var Input_Buffer[32] = 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0;
/************************************************************/
/* Interrupt Vector Table Entries */
/************************************************************/
.section/code IVreset;
jump START;
.section/code IVint4;
jump IVSR0;
.section/code IVint15;
rti;
/************************************************************/
/* Main Routine */
/************************************************************/
.SECTION/code program;
START:
_main:
call Setup_Interrupts;
call Setup_UART;
call Setup_DMA;
_main.end:
START.end:
wait_forever:
idle;
jump wait_forever;
/************************************************************/
/* Programming Interrupts */
/************************************************************/
Setup_Interrupts:
IRPTL = 0x0;
ICNTL = 0x0;
IMASK = 0x0;
iopg=0x0;
ax0=0x0008;
io(0x80)=ax0;
iopg=0x6;
ax0=0x0040;
io(0x202)=ax0;
io(0x203)=ax0;
io(0x204)=ax0;
io(0x205)=ax0;
io(0x206)=ax0;
io(0x207)=ax0;
IOPG = IRQCTL_PAGE;
ar = 0xbbbb;
ar = 0x0;
io(IPR0) = ar;
io(IPR1) = ar;
io(IPR2) = ar;
io(IPR3) = ar;
ENA int; /* Enable Interrupts */
rts;
/************************************************************/
/* Programming For UART */
/************************************************************/
Setup_UART:
/* RESET UART & DMA */
IOPG = UART_IOPAGE;
/* Set LCR to enable access to the Divisor Latch registers */
sr0= UART_LCR_DLAB | UART_LCR_WLS_8 ;
io( UART_LCR )=sr0 ;
nop;
sr0= 0x0001 ; // Set Baud rate to fastest available
io( UART_DLL )=sr0 ;
sr0= 0x0000 ;
io( UART_DLH )=sr0 ;
sr0= UART_LCR_WLS_8 ; // Clear DLAB, keeping width at 8
io( UART_LCR )=sr0 ;
nop;
sr0= 0x0000 ;
io( UART_IER )=sr0 ; // Ensure IER (Interrupt Enable Register) is clear
// setup send and receive interrupt from core
ax0=imask;
ay0= 0x0010 ;
ar=ax0 or ay0;
imask=ar;
ax0=imask;
ay0= 0x8020 ;
ar=ax0 or ay0;
imask=ar;
RTS;
/************************************************************/
/* DMA Controller Programming For UART */
/************************************************************/
Setup_DMA:
/* UART DMA DESCRIPTOR BLOCK RX */
ar= 0x0082; /* Set Direction*/
io(UART_DMA_CONFIG_RX) = ar;
ar = rcv_ddb; /* Next Descriptor Pntr Reg */
dm(rcv_ddb + 4) = ar;
ar = LENGTH(Input_Buffer); /* DMA Memory Count */
dm(rcv_ddb + 3) = ar;
ar = Input_Buffer; /* DMA Memory Address */
dm(rcv_ddb + 2) = ar;
ar = 0x0; /* DMA Memory Page */
dm(rcv_ddb + 1) = ar;
ar = 0x8007; /* Enable DMA, interrupt */
dm(rcv_ddb) = ar;
/* DMA CONFIG */
ar = rcv_ddb; /*NEXT Descriptor */
io(UART_DMA_NEXT_DESCR_RX)=ar;
/* Signify DMA Descriptor Ready */
ar=0x0001;
io(UART_DMA_DESCR_RDY_RX) = ar; /* DMA Descriptor Ready */
nop;
ar= 0x0083; /* Set Direction*/
io(UART_DMA_CONFIG_RX) = ar;
RTS;
/************************************************************/
/* Interrupt Service Routine for the DMA Receive */
/************************************************************/
IVSR0:
ay1 = IOPG;
IOPG = UART_IOPAGE;
ar = 3; /* retire interrupts */
io(UART_DMA_IRQSTAT_RX)=ar;
ar = 0x8007; /* Enable DMA, interrupt */
dm(rcv_ddb) = ar;
ar=0x0001;
io(UART_DMA_DESCR_RDY_RX) = ar;
IOPG = ay1;
rti;
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