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void Init_Sport0(void)
{
// Sport0 receive configuration
// External CLK, External Frame sync, MSB first
*pSPORT0_RCR1 = LRFS; // frame sync signal is active low.
*pSPORT0_RCR2 = SLEN_8;
// Sport0 transmit configuration
// External CLK, External Frame sync, MSB first
*pSPORT0_TCR1 = LTFS; // frame sync signal is active low.
*pSPORT0_TCR2 = SLEN_8;
// Enable MCM 64 transmit & receive channels
*pSPORT0_MTCS0 = 0xFFFFFFFF;
*pSPORT0_MTCS1 = 0xFFFFFFFF;
*pSPORT0_MRCS0 = 0xFFFFFFFF;
*pSPORT0_MRCS1 = 0xFFFFFFFF;
// Set MCM configuration register and enable MCM mode
*pSPORT0_MCMC1 = 0x7000;
*pSPORT0_MCMC2 = 0x001c;
}
//--------------------------------------------------------------//
// Function: Init_DMA //
// //
// Description: Initialize DMA1 in autobuffer mode to receive //
// and DMA2 in autobuffer mode to transmit //
//--------------------------------------------------------------//
void Init_DMA(void)
{
// Set up DMA1 to receive
// Map DMA1 to Sport0 RX
*pDMA1_PERIPHERAL_MAP = 0x1000;
// Configure DMA1
// Write, 8-bit transfers, Interrupt on completion, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_8 | DI_EN | FLOW_1;
// Start address of data buffer
*pDMA1_START_ADDR = RxBuffer;
// DMA inner loop count
*pDMA1_X_COUNT = 64;
// Inner loop address increment
*pDMA1_X_MODIFY = 1;
// Set up DMA2 to transmit
// Map DMA2 to Sport0 TX
*pDMA2_PERIPHERAL_MAP = 0x2000;
// Configure DMA2
// 8-bit transfers, Autobuffer mode
*pDMA2_CONFIG = WDSIZE_8 | FLOW_1;
// Start address of data buffer
*pDMA2_START_ADDR = TxBuffer;
// DMA inner loop count
*pDMA2_X_COUNT =64;
// Inner loop address increment
*pDMA2_X_MODIFY = 1;
}
void Init_Sport_Interrupts(void)
{
*pSIC_IAR0 = 0xffffffff;
*pSIC_IAR1 = 0xffffff2f; // Set Sport0 RX (DMA1) int priority to 2 = IVG9
*pSIC_IAR2 = 0xffffffff;
// assign ISRs to interrupt vectors Sport0 RX ISR -> IVG 9
register_handler(ik_ivg9, Sport0_RX_ISR);
// enable Sport0 RX interrupt
*pSIC_IMASK = 0x00000200;// Sport0 RX
ssync();
}
void Enable_DMA_Sport0(void)
{
// enable DMAs
*pDMA2_CONFIG = (*pDMA2_CONFIG | DMAEN);
*pDMA1_CONFIG = (*pDMA1_CONFIG | DMAEN);
// enable Sport0 TX and RX
*pSPORT0_TCR1 = (*pSPORT0_TCR1 | TSPEN);
*pSPORT0_RCR1 = (*pSPORT0_RCR1 | RSPEN);
}
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