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Internal M2-accessible multicore bus (MQBus)
— QBus protocol multi-master bus connects the four SC140 cores to the M2 memory
— Data bus access of up to 128-bit read and 64-bit write
— Operation at the SC140 core frequency
— A central efficient round-robin arbiter controlling SC140 core access on the MQBus
— Atomic operation control of access to M2 memory by the four SC140 cores and the local bus
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