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/** Don't use TI CSL I2C read/write functions !!! */
#include "csl_i2c.h"#include "5509.h" // registers definition header file
#define I2C_OWN_ADDRESS 0x2F //[101111] own address - don't care if master
#define I2C_TIMEOUT 3000
#define CPU_FREQ 32// function prototypes
void Init_I2C(unsigned short master);
int Read_I2C(unsigned short *data,int length,int master,
unsigned short slaveaddress,int transfermode,int timeout, int checkbus);
int Write_I2C(unsigned short *data,int length,int master,
unsigned short slaveaddress,int transfermode,int timeout);
void IC2_readboot(void);
int IC2_writeboot(void);#define BOOT_LEN 6
// test array
unsigned short DSPBootTable[BOOT_LEN]={0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF};
unsigned short wait_cycles = 10000;
unsigned short buf[3];
unsigned short rbuf[BOOT_LEN];/*---------------------------------------------------------------*/
void Init_I2C(unsigned short master)
{
unsigned short i = 0;
Uint16 IPSC_calc;
I2C_FSET(I2CMDR,IRS,0); // reset I2C
I2C_RSET(I2CMDR,0); // set own address
I2C_FSET(I2CMDR,MST, master); // set master or slave mode
// calculating the IPSC value
IPSC_calc = (CPU_FREQ)/12; //[spru146A;p5,p37]
I2C_RSET(I2CPSC,IPSC_calc);
// Setup clock control registers (100KHz clock out)
I2C_RSET(I2CCLKL, 50);
I2C_RSET(I2CCLKH, 50);
I2C_FSET(I2CMDR,IRS,1); // start I2C
while (i++ < wait_cycles); // wait
}
/*---------------------------------------------------------------*/
int Read_I2C(unsigned short *data,int length,int master,
unsigned short slaveaddress,int transfermode,int timeout, int checkbus)
{
int i, m;
/* set in receive mode */
I2C_FSET(I2CMDR,TRX,0);
I2C_RSET(I2CCNT,length); /* set the count register */
I2C_RSET(I2CSAR,slaveaddress); /* specify slave address */
if (1 == master) {
I2C_FSET(I2CMDR,MST,1); /* turn master mode on */
/* setting the transfer mode */
if (1 == transfermode) { /* S-A-D..(n)..D-P mode */
I2C_FSET(I2CMDR,RM,0);
I2C_FSET(I2CMDR,STP,1);
} else if (2 == transfermode) { /* S-A-D..(n)..D mode (repeat n times)*/
I2C_FSET(I2CMDR,RM,0);
I2C_FSET(I2CMDR,STP,0);
} else if (3 == transfermode) { /* S-A-D-D-D ... (repeat continuous) mode */
I2C_FSET(I2CMDR,RM,1);
I2C_FSET(I2CMDR,STP,0);
} else { /* if user specifies something else, go to 1-st mode S-A-D..(n)..D-P */
I2C_FSET(I2CMDR,RM,0);
I2C_FSET(I2CMDR,STP,1);
}
}
else I2C_FSET(I2CMDR,MST,0); /* if not master, set to slave */I2C_FSET(I2CMDR,STT,1);
for (i = 0; i < length ; i++)
for (m = 0; m <= timeout; m++)/* check for DRR status */
if (1 == I2C_FGET(I2CSTR,RRDY)) break;
if (m >= timeout) return 4; /* time out for transmit DRR ready */
data[i] = I2C_RGET(I2CDRR); /* get next data value from DDR */
}
return 0;
}
/*---------------------------------------------------------------*/
int Write_I2C(unsigned short *data,int length,int master,
unsigned short slaveaddress,int transfermode,int timeout)
{
int i, m;
/* set in transmit mode */
I2C_FSET(I2CMDR,TRX,1);
I2C_RSET(I2CCNT,length); /* set the count register */
I2C_RSET(I2CSAR,slaveaddress); /* specify slave address */
if (1 == master) {
I2C_FSET(I2CMDR,MST,1); /* turn master mode on */
/* setting the transfer mode */
if (1 == transfermode) { /* S-A-D..(n)..D-P mode */
I2C_FSET(I2CMDR,RM,0);
I2C_FSET(I2CMDR,STP,1);
} else if (2 == transfermode) {/* S-A-D..(n)..D mode (repeat n times)*/
I2C_FSET(I2CMDR,RM,0);
I2C_FSET(I2CMDR,STP,0);
} else if (3 == transfermode) { /* S-A-D-D-D ... (repeat continuous) mode */
I2C_FSET(I2CMDR,RM,1);
I2C_FSET(I2CMDR,STP,0);
} else { /* if user specifies something else, go to idle mode */
I2C_FSET(I2CMDR,RM,0);
I2C_FSET(I2CMDR,STP,0);
}
}
else I2C_FSET(I2CMDR,MST,0); /* if not master, set to slave */I2C_FSET(I2CMDR,STT,1);
for (i = 0; i < length ; i++) {
I2C_RSET(I2CDXR,data[i]); /* put next data value in DXR */
for (m = 0; m <= timeout; m++) /* check for DRR status */
if (I2C_FGET(I2CSTR,XRDY) == 1) break;
if (m >= timeout) return 4; /* time out for transmit DRR ready */
}
return 0;
}
/*---------------------------------------------------------------*/
void IC2_readboot()
{
unsigned short k = 0;
buf[0] = 0;
buf[1] = 0;
Write_I2C(buf, 2, 1, 0x50, 1, wait_cycles);
while (k++ < wait_cycles); // wait
Read_I2C(rbuf, BOOT_LEN, 1, 0x50, 1, wait_cycles, 0);
}
/*---------------------------------------------------------------*/
int IC2_writeboot()
{
unsigned short i, k;
for (i = 0; i < BOOT_LEN; i++){
buf[0] = (unsigned short)((unsigned short)(i>>8) & 0xFF);
buf[1] = (unsigned short)(i & 0xFF);
buf[2] = DSPBootTable[i];
Write_I2C(buf, 3, 1, 0x50, 1, wait_cycles);
k = 0;
while (k++ < wait_cycles); // wait
Write_I2C(buf, 2, 1, 0x50, 1, wait_cycles);
k = 0;
while (k++ < wait_cycles); // wait
Read_I2C(buf, 1, 1, 0x50, 1, wait_cycles, 0);
k = 0;
while (k++ < wait_cycles); // wait
rbuf[i] = buf[0];
if (rbuf[i] != DSPBootTable[i])
{
return 99;
}
}
return 0;
}
/*---------------------------------------------------------------*/
void main()
{
CSL_init();
Init_I2C(1);
IC2_writeboot();
IC2_readboot();
}
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