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Например так:
;/*------------------------------------------------------------------*/
;/* McBSP0 Registers */
;/* See TMS320VC5502 Data Manual (SPRS166E), page 120
;/*------------------------------------------------------------------*/
DRR1_0 .set 2800h
DRR2_0 .set 2801h
DXR1_0 .set 2802h
DXR2_0 .set 2803h
SPCR1_0 .set 2804h
SPCR2_0 .set 2805h
RCR1_0 .set 2806h
RCR2_0 .set 2807h
XCR1_0 .set 2808h
XCR2_0 .set 2809h
SRGR1_0 .set 280ah
SRGR2_0 .set 280bh
MCR1_0 .set 280ch
MCR2_0 .set 280dh
RCERA_0 .set 280eh
RCERB_0 .set 280fh
XCERA_0 .set 2810h
XCERB_0 .set 2811h
PCR_0 .set 2812h
;.set 2813h
RCERC_0 .set 2814h
RCERD_0 .set 2815h
XCERC_0 .set 2816h
XCERD_0 .set 2817h
RCERE_0 .set 2818h
RCERF_0 .set 2819h
XCERE_0 .set 281Ah
XCERF_0 .set 281Bh
RCERG_0 .set 281Ch
RCERH_0 .set 281Dh
XCERG_0 .set 281Eh
XCERH_0 .set 281Fh
;/*------------------------------------------------------------------*/
;/* McBSP0_Initialize() */
;/*------------------------------------------------------------------*/
_McBSP0_Initialize:
mov #0000h,port(#SPCR1_0)
mov #0000h,port(#SPCR2_0)
mov #0000h,port(#RCR1_0)
mov #0000h,port(#RCR2_0)
mov #0000h,port(#XCR1_0)
mov #0000h,port(#XCR2_0)
mov #0001h,port(#SRGR1_0)
mov #2000h,port(#SRGR2_0)
mov #0000h,port(#MCR1_0)
mov #0000h,port(#MCR2_0)
mov #0000h,port(#RCERA_0)
mov #0000h,port(#RCERB_0)
mov #0000h,port(#RCERC_0)
mov #0000h,port(#RCERD_0)
mov #0000h,port(#RCERE_0)
mov #0000h,port(#RCERF_0)
mov #0000h,port(#RCERG_0)
mov #0000h,port(#RCERH_0)
mov #0000h,port(#XCERA_0)
mov #0000h,port(#XCERB_0)
mov #0000h,port(#XCERC_0)
mov #0000h,port(#XCERD_0)
mov #0000h,port(#XCERE_0)
mov #0000h,port(#XCERF_0)
mov #0000h,port(#XCERG_0)
mov #0000h,port(#XCERH_0)
mov #0000h,port(#PCR_0)
rpt #3ffh
nop
; ***** SPCR1 ***** (Serial Port Control Register 1)
;0~~~ ~~~~ ~~~~ ~~~~ DLB * RW Digital Loopback Mode (0 off)
;~00~ ~~~~ ~~~~ ~~~~ RJUST * RW Receive Sign-Extension and Justify Mode (00 RJ+ZF)
;~~~0 0~~~ ~~~~ ~~~~ CLKSTP ** RW Clock Stop Mode (SPImode, 0 is off)
;~~~~ ~000 ~~~~ ~~~~ Reserved - R
;~~~~ ~~~~ 0~~~ ~~~~ DXENA * RW DX enabler (0 is off)
;~~~~ ~~~~ ~0~~ ~~~~ Reserved - R (was ABIS in 54xx)
;~~~~ ~~~~ ~~00 ~~~~ RINTM ** RW Receive Interrupt Mode (00 is driven by RRDY transition)
;~~~~ ~~~~ ~~~~ 0~~~ RSYNERR * RW Receive Syncronisation Error (0-No RSYNC error)
;~~~~ ~~~~ ~~~~ ~0~~ RFULL - R Receive Shift Register is full (0-no overrun)
;~~~~ ~~~~ ~~~~ ~~0~ RRDY - R Receiver Ready
;~~~~ ~~~~ ~~~~ ~~~0 RRST *! RW Receiver Reset (0 receiver is in reset)
;0000 0000 0000 0000
MOV #0000h, port(#SPCR1_0)
; ****** SPCR2 ****** (Serial Port Control Register 2)
;0000 00~~ ~~~~ ~~~~ Reserved - R
;~~~~ ~~0~ ~~~~ ~~~~ FREE ? RW Free running mode (1 is ON)
;~~~~ ~~~0 ~~~~ ~~~~ SOFT ? RW Soft mode (0 is disabled)
;~~~~ ~~~~ 0~~~ ~~~~ FRST *! RW Frame Sync generator Reset (0 - FSG is in reset)
;~~~~ ~~~~ ~0~~ ~~~~ GRST *! RW Sample Rate Generator Reset (0 - SRGR is in reset)
;~~~~ ~~~~ ~~00 ~~~~ XINTM * RW Transmit Interrupt Mode (XINT is driven by XRDY transition)
;~~~~ ~~~~ ~~~~ 0~~~ XSYNCERR* RW Transmit Syncronisation Error (0 - no error)
;~~~~ ~~~~ ~~~~ ~0~~ XEMPTY - R Transmitted Shift register is empty
;~~~~ ~~~~ ~~~~ ~~0~ XRDY - R Transmitter is ready
;~~~~ ~~~~ ~~~~ ~~~0 XRST *! RW Transmitter Reset (0 transmitter is in reset)
;0000 0000 0000 0000
MOV #0000h, port(#SPCR2_0)
; ***** PCR ***** (Pin Control Register)
;0~~~ ~~~~ ~~~~ ~~~~ Reserved R
;~0~~ ~~~~ ~~~~ ~~~~ IDLEEN * RW Idle Enable Bit (5509/5510 only)
;~~0~ ~~~~ ~~~~ ~~~~ XIOEN * RW Transmitter GPIO mode when XRST=0
;~~~0 ~~~~ ~~~~ ~~~~ RIOEN * RW Receiver GPIO mode when RRST=0
;~~~~ 1~~~ ~~~~ ~~~~ FSXM * RW Transmit FrameSync mode (0 is external) - GPIO output
;~~~~ ~0~~ ~~~~ ~~~~ FSRM * RW Receive FrameSync mode (0 is external)
;~~~~ ~~0~ ~~~~ ~~~~ CLKXM * RW Transmitter clock mode (0 external clock) - GPIO output
;~~~~ ~~~0 ~~~~ ~~~~ CLKRM * RW Receiver Clock mode (0 external clock)
;~~~~ ~~~~ 0~~~ ~~~~ SCLKME *! RW Sample rate generator input clock mode (See CLKSM)
;~~~~ ~~~~ ~0~~ ~~~~ CLKS_STAT- R CLKS pin status bit
;~~~~ ~~~~ ~~0~ ~~~~ DX_STAT - R DX pin status bit
;~~~~ ~~~~ ~~~0 ~~~~ DR_STAT - R DR pin status bit.
;~~~~ ~~~~ ~~~~ 1~~~ FSXP *! RW Transmit frame-sync polarity bit (1 - active low)
;~~~~ ~~~~ ~~~~ ~1~~ FSRP *! RW Receive frame-sync polarity bit. (1 - active low)
;~~~~ ~~~~ ~~~~ ~~0~ CLKXP * RW Tx clock polarity bit (0 - Change Data Line on Rise)
;~~~~ ~~~~ ~~~~ ~~~0 CLKRP * RW Receive clock polarity bit (0 - read line on falling edge)
;0000 1000 0000 1100
MOV #080Ch, port(#PCR_0)
; ***** RCR1 ***** (Receive Control Register 1)
;0~~~ ~~~~ ~~~~ ~~~~ Reserved - R
;~000 0000 ~~~~ ~~~~ RFRLEN1 * RW Receive Frame length 1 (n+1 words per frame)
;~~~~ ~~~~ 000~ ~~~~ RWDLEN1* RW Receive Word length 1 (000 is 8 bits)
;~~~~ ~~~~ ~~~0 0000 Reserved - R
;0000 0000 0000 0000
MOV #0000h, port(#RCR1_0)
; ***** RCR2 ***** (Receive Control Register 2)
;0~~~ ~~~~ ~~~~ ~~~~ RPHASE * RW Receive Phases (0 - single-phase frame)
;~000 0000 ~~~~ ~~~~ RFRLEN2 * RW Receive Frame length
;~~~~ ~~~~ 000~ ~~~~ RWDLEN2* RW Receive Word length
;~~~~ ~~~~ ~~~0 1~~~ RCOMPAND* RW Receive companding mode
;~~~~ ~~~~ ~~~~ ~0~~ RFIG * RW Receive frame ignore
;~~~~ ~~~~ ~~~~ ~~00 RDATDLY * RW Receive data delay
;0000 0000 0000 1000
MOV #0008h, port(#RCR2_0)
; ***** XCR1 ***** (Transmit Control Register 1)
;0~~~ ~~~~ ~~~~ ~~~~ Reserved - R
;~000 0000 ~~~~ ~~~~ XFRLEN1 * RW Transmit Frame length 1
;~~~~ ~~~~ 000~ ~~~~ XWDLEN1* RW Transmit Word length 1
;~~~~ ~~~~ ~~~0 0000 Reserved - R
;0000 0000 0000 0000
MOV #0000h, port(#XCR1_0)
; ***** XCR2 ***** (Transmit Control Register 2)
;0~~~ ~~~~ ~~~~ ~~~~ XPHASE * RW Transmit Phases (0- single phase frame)
;~000 0000 ~~~~ ~~~~ XFRLEN2 * RW Transmit Frame length 1
;~~~~ ~~~~ 000~ ~~~~ XWDLEN2* RW Transmit Word length 1
;~~~~ ~~~~ ~~~0 1~~~ XCOMPAND* RW Transmit companding
;~~~~ ~~~~ ~~~~ ~0~~ XFIG * RW Transmit frame ignore
;~~~~ ~~~~ ~~~~ ~~00 XDATDLY * RW Transmit data delay
;0000 0000 0000 1000
MOV #0008h, port(#XCR2_0)
; ***** SRGR1 ***** (Sample Rate Generator Register 1)
;0000 0111 ~~~~ ~~~~ FWID * RW Frame Width
;~~~~ ~~~~ 1111 1111 CLKGDV * RW Sample Rate Generator clock divider
;0000 0111 1111 1111
MOV #07FFh, port(#SRGR1_0) ;
; ***** SRGR2 ***** (Sample Rate Generator Register 2)
;0~~~ ~~~~ ~~~~ ~~~~ GSYNC - RW SRG Clock syncronization (used when external SRGR)
;~0~~ ~~~~ ~~~~ ~~~~ CLKSP - RW CLKS Polarity Clock Edge Select
;~~1~ ~~~~ ~~~~ ~~~~ CLKSM *! RW SRGR Clock mode (CLKSM, SCLKME) 0-ext 1-CPU
;~~~0 ~~~~ ~~~~ ~~~~ FSGM * RW SRGR transmit FrameSync mode !!!!! 1-can be regulated, but non-stop Tx
;~~~~ 0000 0000 1111 FPER ? RW Frame period (1 to 4096)
;0010 0000 0000 1111
MOV #200Fh, port(#SRGR2_0) ;
OR #00C0h, port(#SPCR2_0) ; enable SR & FSR generators
RPT #0FFFFh
NOP
; It is _very_ important to do this _after_ all settings are completed
OR #0001h, port(#SPCR1_0) ; Leave Reset Mode
OR #0001h, port(#SPCR2_0) ; Leave Reset Mode
;AND #~(00C0h), port(#SPCR2_0) ; Reset Mode ( Stop CLK )
; Enable XINT0 interrupt
;~~~~ ~~~~ ~~~~ ~~X~ of IER1
OR #0002h, mmap(IER1)
; Enable RINT0 interrupt
;~~~~ ~~~~ ~~X~ ~~~~ of IER0
OR #0020h, mmap(IER0)
MOV #0,T0
RET
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