[an error occurred while processing this directive]
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вот, выдержка из мануала
Assuming that a maskable interrupt does not occur during the delay slots of
a branch (this includes conditional branches that do not complete execution
due to a false condition), the following conditions must be met to process a
maskable interrupt:
The global interrupt enable bit (GIE) bit in the control status register (CSR) is
set to1.
The NMIE bit in the interrupt enable register (IER) is set to1.!!!
The corresponding interrupt enable (IE) bit in the IER is set to1.
The corresponding interrupt occurs, which sets the corresponding bit in
the IFR to 1 and there are no higher priority interrupt flag (IF) bits set in the
IFR.
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