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"When the PPI_CLK is not free-running, there may be additional
latency cycles before data gets received or transmitted. In RX and
TX modes, there may be at least 2 cycles latency before valid data is
received or transmitted."
Стр. 343: http://www.analog.com/UploadedFiles/Associated_Docs/4206716165649BF537_HRM_whole_book_o.pdf.
В мануале на BF531 подобной фразы не нашел, но т.к. ядро одно и то же, наверное и свойства PPI_CLK те же.
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