During a SDRAM read, the selected bank is activated with the row address during the ACTV command. In this example (which is described in a future document), three read commands are performed to three different column addresses in the same page. The EMIF uses a CAS latency of 2 or 3 and a burst length of 4. The 3-cycle read latency causes data to appear 3 cycles after the corresponding column address. Since the default burst length is four words, the SDRAM returns four pieces of data for every read command. If no
additional accesses are pending to the EMIF, as in Figure 2 20, the read burst completes and the unneeded data is disregarded.