//***********************************************************************
section("L1_code") void CacheInit(void)
{
#ifdef DATA_CACHE_EN
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_LOCK | CPLB_VALID)
#define L1_DMEMORY (PAGE_SIZE_1MB | CPLB_SUPV_WR | CPLB_LOCK | CPLB_VALID)
//#ifdef DCACHE_WB
#define SDRAM_DGENERIC_WB (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID)
//#else
#define SDRAM_DGENERIC_WT (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID)
//#endif
*pDMEM_CONTROL = ENDM;
csync();
*pDCPLB_ADDR0=(void *)0xFF900000;
*pDCPLB_DATA0=L1_DMEMORY;
*pDCPLB_ADDR1=(void *)0x00000000;
*pDCPLB_DATA1=SDRAM_DGENERIC_WB;
*pDCPLB_ADDR2=(void *)0x00400000;
*pDCPLB_DATA2=SDRAM_DGENERIC_WB;
*pDCPLB_ADDR3=(void *)0x00800000;
*pDCPLB_DATA3=SDRAM_DGENERIC_WB;
*pDCPLB_ADDR4=(void *)0x00C00000;
*pDCPLB_DATA4=SDRAM_DGENERIC_WT;
//*pDCPLB_ADDR5=(void *)0;
*pDCPLB_DATA5=0;
//*pDCPLB_ADDR6=(void *)0;
*pDCPLB_DATA6=0;
//*pDCPLB_ADDR7=(void *)0;
*pDCPLB_DATA7=0;
//*pDCPLB_ADDR8=(void *)0;
*pDCPLB_DATA8=0;
//*pDCPLB_ADDR9=(void *)0;
*pDCPLB_DATA9=0;
//*pDCPLB_ADDR10=(void *)0;
*pDCPLB_DATA10=0;
//*pDCPLB_ADDR11=(void *)0;
*pDCPLB_DATA11=0;
//*pDCPLB_ADDR12=(void *)0;
*pDCPLB_DATA12=0;
//*pDCPLB_ADDR13=(void *)0;
*pDCPLB_DATA13=0;
//*pDCPLB_ADDR14=(void *)0;
*pDCPLB_DATA14=0;
//*pDCPLB_ADDR15=(void *)0;
*pDCPLB_DATA15=0;
*pDMEM_CONTROL=(ENDM | ENDCPLB | ACACHE_BSRAM);
csync();
#endif
#ifdef INSTR_CACHE_EN
#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | 0x0200 | CPLB_USER_RD | CPLB_VALID)
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
//#define SRAM_IGENERIC (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
//#define SRAM_INON_CHBL (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID)
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_LOCK | CPLB_VALID)
*pIMEM_CONTROL = ENIM;
csync();
*pICPLB_ADDR0=(void *)0xFFA00000;
*pICPLB_DATA0=L1_IMEMORY;
*pICPLB_ADDR1=(void *)0x00000000; //sdram0
*pICPLB_DATA1=SDRAM_INON_CHBL;
*pICPLB_ADDR2=(void *)0x00400000; //sdram1
*pICPLB_DATA2=SDRAM_IGENERIC;
*pICPLB_ADDR3=(void *)0x00800000; //sdram2
*pICPLB_DATA3=SDRAM_INON_CHBL;
*pICPLB_ADDR4=(void *)0x00C00000; //sdram3
*pICPLB_DATA4=SDRAM_INON_CHBL;
//*pICPLB_ADDR5=(void *)0x00000000;
*pICPLB_DATA5=0;
//*pICPLB_ADDR5=(void *)0x00000000;
*pICPLB_DATA6=0;
//*pICPLB_ADDR5=(void *)0x00000000;
*pICPLB_DATA6=0;
//*pICPLB_ADDR7=(void *)0x00000000;
*pICPLB_DATA7=0;
//*pICPLB_ADDR8=(void *)0x00000000;
*pICPLB_DATA8=0;
//*pICPLB_ADDR9=(void *)0x00000000;
*pICPLB_DATA9=0;
//*pICPLB_ADDR10=(void *)0x00000000;
*pICPLB_DATA10=0;
//*pICPLB_ADDR11=(void *)0x00000000;
*pICPLB_DATA11=0;
//*pICPLB_ADDR12=(void *)0x00000000;
*pICPLB_DATA12=0;
//*pICPLB_ADDR13=(void *)0x00000000;
*pICPLB_DATA13=0;
//*pICPLB_ADDR14=(void *)0x00000000;
*pICPLB_DATA14=0;
//*pICPLB_ADDR15=(void *)0x00000000;
*pICPLB_DATA15=0;
*pIMEM_CONTROL=(ENIM | IMC | ENICPLB);
csync();
#endif
}