Six ALU (32-/40-Bit) Functional Units
Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
Supports up to Two Floating Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle
Two Multiply Functional Units
Mixed-Precision IEEE Floating Point Multiply Supported up to:
2 SP × SP -> SP Per Clock
2 SP × SP -> DP Every Two Clocks
2 SP × DP -> DP Every Three Clocks
2 DP × DP -> DP Every Four Clocks
Fixed Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Comples Multiples