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When the PFx pins are configured as slave-select outputs, the value which is driven onto these outputs depends on the value of the CPHA bit in the SPICTLx register. If CPHA=1 , the value is set by software control of the FLG bits. If CPHA=0 , the value is determined by the SPI hardware, and the FLG bits are ignored.
When CPHA=1 , the SPI protocol permits the slave-select line to either
remain asserted (low) or be de-asserted between transferred words. This requires the user to write to the SPIFLGx register, setting or clearing the appropriate FLG bits as needed. For example, to drive PF3 as a slave-select, Serial Peripheral Interface (SPI) Ports FLS1 in SPIFLG1 must be set. Clearing FLG1 in SPIFLG1 will drive PF3 low;
setting FLG1 will drive PF3 high. If needed, PF3 can be cycled high and low between transfers by setting FLG1 and then clearing FLG1 ; otherwise, PF3 will remain active (low) between transfers.
When CPHA=0 , the SPI protocol requires that the slave-select be de-asserted between transferred words. In this case, the SPI hardware controls the pins. For example, to use PF3 as a slave-select pin, it is only necessary to set the FLS1 bit in the SPIFLG1 register. Writing to the FLG1 bit is not required, because the SPI hardware automatically drives the PF3 pin.
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