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tms320f2812.pdf:
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Table 46. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
TIMER0TIM 0x00 0C00 1 CPU-Timer 0, Counter Register
TIMER0TIMH 0x00 0C01 1 CPU-Timer 0, Counter Register High
TIMER0PRD 0x00 0C02 1 CPU-Timer 0, Period Register
TIMER0PRDH 0x00 0C03 1 CPU-Timer 0, Period Register High
TIMER0TCR 0x00 0C04 1 CPU-Timer 0, Control Register
reserved 0x00 0C05 1
TIMER0TPR 0x00 0C06 1 CPU-Timer 0, Prescale Register
TIMER0TPRH 0x00 0C07 1 CPU-Timer 0, Prescale Register High
TIMER1TIM 0x00 0C08 1 CPU-Timer 1, Counter Register
TIMER1TIMH 0x00 0C09 1 CPU-Timer 1, Counter Register High
TIMER1PRD 0x00 0C0A 1 CPU-Timer 1, Period Register
TIMER1PRDH 0x00 0C0B 1 CPU-Timer 1, Period Register High
TIMER1TCR 0x00 0C0C 1 CPU-Timer 1, Control Register
reserved 0x00 0C0D 1
TIMER1TPR 0x00 0C0E 1 CPU-Timer 1, Prescale Register
TIMER1TPRH 0x00 0C0F 1 CPU-Timer 1, Prescale Register High
TIMER2TIM 0x00 0C10 1 CPU-Timer 2, Counter Register
TIMER2TIMH 0x00 0C11 1 CPU-Timer 2, Counter Register High
TIMER2PRD 0x00 0C12 1 CPU-Timer 2, Period Register
TIMER2PRDH 0x00 0C13 1 CPU-Timer 2, Period Register High
TIMER2TCR 0x00 0C14 1 CPU-Timer 2, Control Register
reserved 0x00 0C15 1
TIMER2TPR 0x00 0C16 1 CPU-Timer 2, Prescale Register
TIMER2TPRH 0x00 0C17 1 CPU-Timer 2, Prescale Register High
reserved 0x00 0C18
0x00 0C3F
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Overview 1-12 SPRU065 (TMS320F28x Event Manager (EV) Peripheral Reference Guide)
1.3 Event Manager (EV) Register Addresses
Table 1–2 displays the addresses of the event manager registers.
Table 1–2. EVA Registers†
Name Address Range Description
GPTCONA 0x0000–7400 GP Timer Control Register A
T1CNT 0x0000–7401 GP Timer 1 Counter Register
T1CMPR 0x0000–7402 GP Timer 1 Compare Register
T1PR 0x0000–7403 GP Timer 1 Period Register
T1CON 0x0000–7404 GP Timer 1 Control Register
T2CNT 0x0000–7405 GP Timer 2 Counter Register
T2CMPR 0x0000–7406 GP Timer 2 Compare Register
T2PR 0x0000–7407 GP Timer 2 Period Register
T2CON 0x0000–7408 GP Timer 2 Control Register
EXTCONA‡ 0x0000–7409 GP Extension Control Register A
COMCONA 0x0000–7411 Compare Control Register A
ACTRA 0x0000–7413 Compare Action Control Register A
DBTCONA 0x0000–7415 Dead-Band Timer Control Register A
CMPR1 0x0000–7417 Compare Register 1
CMPR2 0x0000–7418 Compare Register 2
CMPR3 0x0000–7419 Compare Register 3
CAPCONA 0x0000–7420 Capture Control Register A
CAPFIFOA 0x0000–7422 Capture FIFO Status Register A
CAP1FIFO 0x0000–7423 Two-Level Deep Capture FIFO Stack 1
CAP2FIFO 0x0000–7424 Two-Level Deep Capture FIFO Stack 2
CAP3FIFO 0x0000–7425 Two-Level Deep Capture FIFO Stack 3
CAP1FBOT 0x0000–7427 Bottom Register Of Capture FIFO Stack 1
† The EV-B register set is identical except the address range is from 0x0000–7500 to 0x0000–753F. The registers in this table
are mapped to Zone 2. This space allows only 16-bit accesses. 32-bit accesses produce undefined results.
‡ New register compared to 240x
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