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V odnom komponente navernae net, tak kak adressnoe prostranstvo CS0, CS2 i CS3 kajdoe tol^ko po 16 MBytes. Ostavliat^ DSP voobsche bez external memory ne ochen^ krasivo po otnosheniu k DSP. A poluchit^ po timing - external memory cherez FPGA navernoe slojno.
Esli uj delat^ SDRAM ili DDR controller na FPGA - ia bi sdelal etot FPGA masterom na Expansion Bus.
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