Отправлено diwil 19 января 2004 г. 17:50 В ответ на: схемку(описание) интересно взглянуть, может там не "обычный счетчик" отправлено yes 19 января 2004 г. 09:11

entity My_mod is
Port (
-- Phase shift control
phaseshift : in std_logic;

-- Global enable
enable : in std_logic;

-- Clock generator signals:
hf_in : in std_logic;
aux_clk : in std_logic;
drive : out std_logic;

lo_in : in std_logic;
lo_drive : out std_logic;
lo_out : inout std_logic;

-- Input signal:
insig : in std_logic;

-- Output detected signals:
i_out : out std_logic_vector(1 downto 0);
q_out : out std_logic_vector(1 downto 0);

-- check phase
p_out : inout std_logic_vector(1 downto 0);

-- Pulse duty detector
dutyout : out std_logic;
dutybase : out std_logic;

-- check ones:

baseout : out std_logic;
basesig : out std_logic
);

end My_mod;

architecture Behavioral of My_mod is
signal d : std_logic_vector(2 downto 0);
signal i : std_logic;
signal q : std_logic;
signal clk : std_logic;

begin
process (aux_clk)
begin
clk <= aux_clk;
end process;

-- Local LF oscillator:
process(lo_in, lo_out)
begin
lo_drive <= not lo_out;
lo_out <= not lo_in;
end process;


-- Internal Phase Module:
process (phaseshift)
begin
if(phaseshift'event and phaseshift = '1') then
p_out <= p_out + 1;
end if;
end process;

-- Internal Shifter
process(clk,d)
begin
if(clk'event and clk = '1') then
d <= d + 1;
q <= d(2) xor d(1);
i <= d(2);
baseout <= clk;
basesig <= d(1);
else
baseout <= clk ;
end if;
end process;

-- Mixer module:
process(hf_in,i)
begin
drive <= hf_in xor i;
end process;

-- Phase detectors:
process (insig, i, q, enable)
begin
i_out(0) <= insig xor i;
i_out(1) <= insig xor not i;
q_out(0) <= insig xor q;
q_out(1) <= insig xor not q;
dutybase <= insig;
dutyout <= not enable;
end process;
end Behavioral;