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стратиксы. У них минимум 6 PLL и вот:
Stratix device enhanced PLLs provide advanced programmable phase
and clock delay shifting. For phase shifting, designers can specify a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. Phase-shifting values in time units are allowed with a resolution range of 160 to 420 ps. This resolution is a function of frequency input and the multiplication and division factors – i.e., it is a function of the VCO period equal to an eighth of the VCO period. Each clock output counter can choose a different phase of the VCO period from up to eight taps. Designers can use this clock output counter along with an initial setting on the post-scale counter to achieve a phase shift range for the entire period of the output clock. The phase tap feedback to the m counter can shift all outputs to a single phase or delay. The Quartus II software automatically sets the phase taps and counter
settings according to the phase shift entered.
In addition to the phase shift feature, the fine tune clock delay shift feature provides advanced time delay shift control on each of the four PLL outputs. Each PLL output shifts in 250-ps increments for a range of –3.0 ns to +3.0 ns between any two outputs using discrete delay elements. Total delay shift between any two PLL outputs must be less than 3 ns. For example, shifts on outputs of –1 and +2 ns is allowed, but not –1 and +2.5 ns. There is some delay variation due to process, voltage, and temperature. Only the clock delay shift blocks can be controlled during system operation for dynamic clock delay control.
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