Отправлено Victor® 25 февраля 2004 г. 10:21 В ответ на: Поделитесь VHDL модулем для реализации MAC (сумматор+умножитель) отправлено Rodionov Sergey 25 февраля 2004 г. 09:02

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
ENTITY mul16 IS
PORT
(
	a			: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
	b			: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
	clk			: IN STD_LOGIC;
	nreset		: IN STD_LOGIC;
	ena			: IN STD_LOGIC;
	noe			: IN STD_LOGIC;
	mul			: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END mul16;
ARCHITECTURE behave OF mul16 IS
SIGNAL a_reg		: STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL b_reg		: STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL mul_reg		: STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Registered A and B values 
PROCESS (clk, nreset)
BEGIN
	IF (nreset = '0') THEN
		a_reg <= (OTHERS => '0');
		b_reg <= (OTHERS => '0');
	ELSIF (clk'EVENT AND clk = '1') THEN
		IF (ena = '1') THEN
			a_reg <= a;
			b_reg <= b;
		END IF;
	END IF;                                            
END PROCESS;
-- Multiplication of registered A and B values
PROCESS (clk, nreset)
BEGIN
	IF (nreset = '0') THEN
		mul_reg <= (OTHERS => '0');
	ELSIF (clk'EVENT AND clk = '1') THEN
		IF (ena = '1') THEN
		mul_reg <= a_reg * b_reg;
		END IF;
	END IF;
END PROCESS;
-- Tri-State MUL output description
PROCESS (mul_reg, noe)
BEGIN
	IF (noe = '0') THEN
		mul <= mul_reg;
	ELSE
		mul <= (OTHERS => 'Z');
	END IF;
END PROCESS;
END behave;