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library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity DLL_USE is
port(
CLK : in std_ulogic;
RST : in std_ulogic;
CLK_DLL_4div : out std_ulogic;
CLK_DLL_normal : out std_ulogic;
CLK_DLL_2x : out std_ulogic;
LOCKED : out std_ulogic
);
end DLL_USE;
architecture DLL_USE of DLL_USE is
component BUFG
port (
I : in std_ulogic;
O : out std_ulogic
);
end component;
component CLKDLL
generic(
CLKDV_DIVIDE : REAL := 2.0
);
port (
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
RST : in std_ulogic := '0';
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
LOCKED : out std_ulogic := '0'
);
end component;
component IBUFG
port (
I : in std_ulogic;
O : out std_ulogic
);
end component;
signal CLK0 : std_ulogic;
signal CLK2x : std_ulogic;
signal NET12 : std_ulogic;
signal NET20 : std_ulogic;
signal NET28 : std_ulogic;
signal NET9 : std_ulogic;
begin
---- Component instantiations ----
U1 : CLKDLL
generic map (
CLKDV_DIVIDE => 4.0 -- change HERE 4.0 for other.
)
port map(
CLK0 => NET12,
CLK2X => NET20,
CLKDV => NET28,
CLKFB => CLK0, -- SET CLK2x for FB
CLKIN => NET9,
RST => RST,
LOCKED => LOCKED
);
U2 : IBUFG
port map(
I => CLK,
O => NET9
);
U3 : BUFG
port map(
I => NET12,
O => CLK0
);
U4 : BUFG
port map(
I => NET20,
O => CLK2x
);
U5 : BUFG
port map(
I => NET28,
O => CLK_DLL_4div
);
CLK_DLL_normal <= CLK0;
CLK_DLL_2x <= CLK2x;
end DLL_USE;
----------------- конец.
Надо сделать в 3.1 HDL макрос, вроде так называется. И вставить это туда.
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