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Отправлено
DM 24 сентября 2001 г. 10:55 |
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process(CE, SetBegAddr)
begin
if SetBegAddr = '1' then
counter1 <= BegAddr_En;
elsif CE'event and CE = '1' then
counter1 <= counter1 + 1;
end if;
end process;
Пишет:
Synthesizing...
Warning L153/C0 : #0 Warning: Variable 'BegAddr_En' is being read in routine FormDiag line 153 in file 'C:/FNDTN/ACTIVE/PROJECTS/TESTPAR1/FormDiag.vhd', but is not in the process sensitivity list of the block which begins there. (HDL-179)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<0>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<1>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<2>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<3>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<4>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<5>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<6>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<7>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<8>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<9>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<10>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<11>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<12>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<13>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<14>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<15>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<16>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
Error L-1/C0 : #0 Error: Sequential mapping has detected that the cell '/FormDiag_OPT/counter1_reg<17>' uses both the asynchronous 'set' and 'clear' pins. The target architecture does not support both on the same sequential device. (FPGA-SEQMAP-2)
18 error(s) 1 warning(s) found
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