Отправлено Amid 20 апреля 2004 г. 15:15

Пытаюсь с помощью DLL-ок умножить частоту тактирования в 4 раза (в Spartan2 (ActiveHDL -ISE5.1)). Cхему собрал, вроде, правильную - компиляция и синтез проходят без проблем. Проблемка возникает при "растусовке" DLL-ок внутри ПЛИС - при помощи "сonstraints" атрибутов и правки UCF-фала все должно было разрешится. Но как-то я не правильно обьявляю атрибуты - синтезатор не понимает ограничения и выдаёт ворнинги :

WARNING:Xst:37 - Unknown property "syn_black_box".
WARNING:Xst:37 - Unknown property "syn_noprune".
WARNING:Xst:37 - Unknown property "xc_alias".
WARNING:Xst:766 - C:/My_Designs/test_ts/src/test_clk_dll.vhd line 148: Generating a Black Box for component .
WARNING:Xst:37 - Unknown property "syn_black_box".
WARNING:Xst:37 - Unknown property "syn_noprune".
WARNING:Xst:37 - Unknown property "xc_alias".
WARNING:Xst:766 - C:/My_Designs/test_ts/src/test_clk_dll.vhd line 162: Generating a Black Box for component .
WARNING:Xst:37 - Unknown property "syn_black_box".
WARNING:Xst:37 - Unknown property "syn_noprune".
WARNING:Xst:37 - Unknown property "xc_alias".
......

соответстсенно при имплиментации выдаются те же ошибки - НЕ МОГУ РАЗВЕСТИ!!!

Ниже текст проги - разьясните, что не так, - если не трудно !!!!

--------------------------

---------------------------------------------------------------------------------------------------
--
-- Title : No Title
-- Design : test_ts
-- Author :
-- Company :
--
---------------------------------------------------------------------------------------------------
--
-- File : C:\My_Designs\test_ts\compile\test.vhd
-- Generated : Thu Apr 1 19:19:46 2004
-- From : C:\My_Designs\test_ts\src\test.bde
-- By : Bde2Vhdl ver. 2.6
--
---------------------------------------------------------------------------------------------------
--
-- Description :
--
---------------------------------------------------------------------------------------------------
-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;

-- other libraries declarations
-- synopsys translate_off
library SPARTAN2;
use SPARTAN2.VPKG.all;
library IEEE;
use IEEE.vital_timing.all;
-- synopsys translate_on

entity test_clk_dll is
port(
clk : in std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
LOCKED : out std_ulogic
);
end test_clk_dll;

architecture test_clk_dll_body of test_clk_dll is

---- Component declarations -----

component BUFG
port (
I : in std_ulogic;
O : out std_ulogic
);
end component;
component CLKDLL
-- synopsys translate_off
generic(
DUTY_CYCLE_CORRECTION : BOOLEAN := TRUE;
STARTUP_WAIT : BOOLEAN := true
);
-- synopsys translate_on
port (
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
RST : in std_ulogic := '0';
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
LOCKED : out std_ulogic := '0'
);
end component;
component IBUFG
port (
I : in std_ulogic;
O : out std_ulogic
);
end component;

--attribute box_type : string;
attribute syn_black_box: boolean;
attribute syn_black_box of IBUFG : component is true;
attribute syn_black_box of BUFG : component is true;
attribute syn_black_box of CLKDLL : component is true;

attribute syn_noprune : boolean;
attribute syn_noprune of IBUFG : component is true;
attribute syn_noprune of BUFG : component is true;
attribute syn_noprune of CLKDLL : component is true;

attribute xc_alias : string;
attribute xc_alias of IBUFG: component is "IBUFG";
attribute xc_alias of BUFG: component is "BUFG";
attribute xc_alias of CLKDLL: component is "CLKDLL";

attribute clkdv_divide : string;
attribute clkdv_divide of clkdll2 : label is "4.0";

--attribute xc_loc : string;
--attribute xc_loc of buf_clk_in : label is "GCLKBUF0";
--attribute xc_loc of clkdll1 : label is "DLL0P";
--attribute xc_loc of buf_clk0_1 : label is "GCLKPAD0";
--attribute xc_loc of clkdll2 : label is "DLL1P";

---- Constants -----
constant GND_CONSTANT : STD_LOGIC := '0';

---- Signal declarations used on the diagram ----

signal GND : STD_LOGIC;
signal CLKDLL1_CLK2X : std_ulogic;
signal clk_out_buf : std_ulogic;
signal locked_out_not : std_ulogic;
signal CLKFB1_out : std_ulogic;
signal locked_out : std_ulogic;
signal CLKDLL1_CLK2X_buf : std_ulogic;
signal CLKDLL2_CLK0_buf : std_ulogic;
signal clkdll1_LOCKED : std_ulogic;
signal CLKDLL2_CLK0 : std_ulogic;
signal CLKDLL1_CLK0 : std_ulogic;

begin

---- Component instantiations ----

CLKDLL1 : CLKDLL
port map(
CLK0 => CLKDLL1_CLK0,
CLK180 => CLK180,
CLK270 => CLK270,
CLK2X => CLKDLL1_CLK2X,
CLK90 => CLK90,
CLKDV => CLKDV,
CLKFB => CLKFB1_out,
CLKIN => clk_out_buf,
LOCKED => clkdll1_LOCKED,
RST => GND
);

buf_clk0_1 : BUFG
port map(
I => CLKDLL1_CLK0,
O => CLKFB1_out
);

buf_clk_in : IBUFG
port map(
I => clk,
O => clk_out_buf
);

CLKDLL2 : CLKDLL
port map(
CLK0 => CLKDLL2_CLK0,
CLK2X => CLK2X,
CLKDV => open,
CLKFB => CLKDLL2_CLK0_buf,
CLKIN => CLKDLL1_CLK2X_buf,
LOCKED => LOCKED,
RST => locked_out_not
);

buf_clk0_2 : BUFG
port map(
I => CLKDLL2_CLK0,
O => CLKDLL2_CLK0_buf
);

buf_clk2x_1 : BUFG
port map(
I => CLKDLL1_CLK2X,
O => CLKDLL1_CLK2X_buf
);

locked_out_not <= not(locked_out);

buf_locked_1 : BUFG
port map(
I => clkdll1_LOCKED,
O => locked_out
);

---- Power , ground assignment ----

GND <= GND_CONSTANT;

end test_clk_dll_body;

• Если поможет, — V61   (20.04.2004 17:53, 257 байт)
  • To V61 - Буду очень благодарен. Ввем спасибо!!! :) — Amid   (20.04.2004 20:39, пустое)
    • Лови. — V61   (21.04.2004 10:50, пустое)
• Атрибуты для другого синтезатора (+) — andrew_b   (20.04.2004 16:40, 378 байт, ссылка)
  • Все хорошо но ... — Amid   (21.04.2004 20:24, 271 байт)