[an error occurred while processing this directive]
|
module D_D_F3 ( OUT ,CLK ,IN );
parameter DEEP = 2 ;
parameter ins = 3;
input CLK ;
input [ins-1:0]IN ;
output [ins-1:0]OUT ;
reg [ins-1:0] delay[DEEP:0];
integer index;
always @(posedge CLK )
begin
for(index=DEEP;index>0;index=index-1)
begin
delay[index]=delay[index-1];
end
delay[0]=IN;
end
assign OUT=delay[DEEP];
endmodule
E-mail: info@telesys.ru