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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shifter is
generic(
width : natural := 16
);
port(
--************* Host interface ************%
clk :in std_logic;
res :in std_logic;
data :in std_logic_vector(15 downto 0);-- Internal buffer register
WR :in std_logic; -- Write register signal.
--************ device interface *************%
SDATA : out std_logic;
SCLK : out std_logic;
FRAME : out std_logic
);
end shifter;
architecture arc of shifter is
signal Dbuf : std_logic_vector(15 downto 0);
--**********************************************
begin
SCLK<=clk;
LD_buf: process(clk)
begin -- data buffer
if clk = '1' and clk'event then
if res='1' then
Dbuf<= (others=>'0');
elsif WR ='1' then
Dbuf<= data;
end if;
end if;
end process;
LBitsCnt: process(clk)
subtype TBitsCnt is integer range 0 to width-1;
variable BitsCnt : TBitsCnt; --counter of sending bits
begin
if clk = '0' and clk'event then
if res='1' then
BitsCnt:=TBitsCnt'high;
FRAME<='1';
SDATA<='0';
elsif WR='1' then
BitsCnt:=TBitsCnt'high;
FRAME<='0';
elsif BitsCnt /= 0 then
BitsCnt:=BitsCnt-1;
SDATA<=Dbuf(BitsCnt);
else
FRAME<='1';
end if;
end if;
end process;
end arc;
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