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--=============================================================================
ENTITY position_latch IS
GENERIC (WIDTH : integer :=16);
PORT (
DATA : IN std_logic_vector (15 downto 0);
RST : IN std_logic;
CLK : IN std_logic;
OE : IN std_logic;
Q : OUT std_logic_vector(15 downto 0)
);
END position_latch ;
--=============================================================================
ARCHITECTURE behv OF position_latch IS
signal Qtmp : std_logic_vector (15 downto 0);
BEGIN
--=============================================================================
PROCESS(Clk,rst,Data)
BEGIN
if(rst = '0') then Qtmp <= "0000000000000000";
elsif (Clk = '1' and Clk'event) then Qtmp <= DATA;
end if;
END PROCESS;
--=============================================================================
PROCESS(CLK, OE, Qtmp)
BEGIN
if (Clk = '1' and Clk'event) then
if(OE='0') then Q <=Qtmp;
else Q <= "ZZZZZZZZZZZZZZZZ";
end if;
end if;
END PROCESS;
--=============================================================================
END behv;
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