Отправлено druzhin 27 мая 2004 г. 09:50 В ответ на: ЕСТЬ!!! ЕСТЬ!!! (+) отправлено druzhin 27 мая 2004 г. 09:44

module new_skn1 ( ainit, DO, CLK2, ENq, SKN1eq, SKN1ad, ENu, new_flag, addrq, addru );

input DO, CLK2, ENq, ENu, SKN1eq, ainit ;
input [3:0] addrq, addru, SKN1ad ;
output wire new_flag ;

reg [15:0] new, f ;
wire [15:0] eq, seq, eu, rq, ru, newt, f_init ;

assign new_flag = |newt ;

genvar i ;
generate for ( i=0 ; i<16 ; i=i+1 ) begin : flag

assign newt[i] = new[i] & seq[i] & SKN1eq ;
assign f_init[i] = f[i] | ainit ;

assign eq[i] = (addrq==i) ;
assign eu[i] = (addru==i) ;
assign seq[i] = (SKN1ad==i) ;
assign rq[i] = (eq[i] & ENq) ;
assign ru[i] = (eu[i] & ENu) ;

always @( posedge CLK2 or posedge f_init[i] )
if (f_init[i]) new[i] <= 0 ; else if (ru[i]) new[i] <= 1 ;

always @( posedge DO or negedge new[i] )
if (~new[i]) f[i] <= 0 ; else if (rq[i]) f[i] <= 1 ;

end endgenerate

endmodule