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Cyclone Device Handbook, Altera Corporation October 2003:
"Cyclone PLLs provide clock synthesis for PLL output ports using
M/(N ~ post-scale) scaling factors. There is one pre-scale divider (N) and one multiply counter (M) per PLL. N and post-scale counter values range from 1 to 32. The M counter ranges from 2 to 32."
"In Cyclone FPGAs, the VCO ranges from 500 to
1,000 MHz."
My~y}p|~p pp, { }w~ tp ~p p{z PLL 500MHz/32 = 15.625MHz.
Nu }s
~y{p{ ~, u} |p r{p p{rp! tp| ~p rt DDS 20MHz, {pxp|
}~wy ~p 20, y rus tu|r.
@ ~pxrp UNX |w~} |! u} q|uu, r tp~~z y
pyy, ~p ~us ~u ~p|wu~ ~y{p{y uqrp~yz {}u tpr|u~y ~p p ty{uyxpyy y xu{p|~} {p~p|u!
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