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Version 4.1 of the Quartus II software extends technology leadership with support for the new Cyclone II FPGA family and new verification, optimization, and ease of use features to deliver the lowest development costs for FPGAs. Table 1 summarizes the new features included in this release.
Verification
In-System Updating of RAM/ROM & Constants
Engineers can now easily perform (what if type experiments in-system in just seconds. Quartus II software enables FPGA memory contents and design constants to be updated in-system without recompiling a design or reconfiguring the rest of the FPGA.
Technology Map Viewer
Designs can now be debugged in Quartus II software after the synthesis step at a detailed level by viewing a logical representation of the design implementations mapped into Altera device primitives. Once the fitting and timing analysis steps have been performed, critical timing paths and timing information can be highlighted in the Technology Map Viewer display. Users can cross probe from timing analysis and other Quartus II tools to the technology map viewer or from the Technology Map Viewer to design source files, the floorplan editor, or Quartus II Chip Editor for design optimization.
SignalTap II Embedded Logic Analyzer Enhancements
The free Quartus II software now includes device configuration and the SignalTap II embedded logic analyzer, allowing easy deployment of in-system logic analysis capabilities to multiple lab locations or field service personnel. The advanced trigger feature now includes an event counter trigger condition function.
Optimization
New Resource & Timing Optimization Advisor Tools
These new tools provide specific advice on resource utilization or design timing performance based on the current design project settings and assignments and provide links to software features to implement the proposed suggestions.
Multiplexor Optimizations Reduce Area Use Up to 20 Percent
Designers using the Quartus II integrated synthesis feature can now reduce device area usage up to 20 percent to fit into a smaller device and save cost. A new optimization technique optimizes multiplexer use to take advantage of Alteraў FPGA architectural features.
Auto Fit Fitter Effort Level Set by Default for New Projects
Provides an average of 40% compile time reductions on designs where timing requirements are satisfied easily.
Stratix II Physical Synthesis Optimization
Physical synthesis optimizations now provide an average of 9% faster performance for Stratix II designs on top of the 50 percent performance gain delivered over Stratix designs compiled without using physical synthesis.
Ease-of-Use
Easier Access to Altera MegaCore Functions
Altera subscriptions now include the MegaCore IP Library and Nios II embedded processor, evaluation edition CDs. These CDs allow you to evaluate all of Altera's MegaCore design-ready IP functions in hardware before purchasing a license for the IP. The Nios II embedded processor CD also includes the new Nios II integrated development environment for C/C++ code development.
Version Support
Gives designers the ability to easily experiment with different versions of design source files and settings. This feature complements the previously introduced revisions feature that allowed designers to maintain separate settings only.
Import/Export Assignments in CSV format
Engineers can now easily transfer assignments between Quartus II software and Excel spreadsheets using the CSV format. This capability can aid in transferring pinout information between PCB design software packages that support interfaces with Excel spreadsheets.
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