Отправлено _гоша 15 августа 2004 г. 15:31

line 22: architecture behavior of quad_top is
Warning: Line 22: File d:\altera\max2work\qencoder_vhd\quad_top.vhd: Unsupported feature warning: Component configurations are not supported. Please see line number 22 in file d:\altera\max2work\qencoder_vhd\quad_top.vhd
Warning: Line 22: File d:\altera\max2work\qencoder_vhd\quad_top.vhd: Unsupported feature warning: Component configurations are not supported. Please see line number 22 in file d:\altera\max2work\qencoder_vhd\quad_top.vhd
Warning: Line 22: File d:\altera\max2work\qencoder_vhd\quad_top.vhd: Unsupported feature warning: Component configurations are not supported. Please see line number 22 in file d:\altera\max2work\qencoder_vhd\quad_top.vhd
Warning: Line 22: File d:\altera\max2work\qencoder_vhd\quad_top.vhd: Unsupported feature warning: Component configurations are not supported. Please see line number 22 in file d:\altera\max2work\qencoder_vhd\quad_top.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.all;
--=============================================================================
entity quad_top is
generic (width   : integer := 16);
    port (
        ChA  : in std_logic;
        ChB  : in std_logic;
        Clk  : in std_logic;
        Rst  : in std_logic;
        OE   : in std_logic;
 		Cnt  : out std_logic;
		Up_Down :out std_logic;
        D    : inout std_logic_vector (width -1 downto 0)
    );
end quad_top;
--=============================================================================
-- line 22:
architecture behavior of quad_top is
signal filt_cha, filt_chb : std_logic;
signal t_count  : std_logic_vector (width -1 downto 0);
signal data_out : std_logic_vector (width -1 downto 0);
signal cnt_en   : std_logic;
signal up_ndown : std_logic;
--=============================================================================
component digital_filter
    port (
      ChA		: in  std_logic;
	  ChB		: in  std_logic;
      Clk		: in  std_logic;
      Rst		: in  std_logic;
	  ChA_filt 	: out std_logic;
      ChB_filt 	: out std_logic
	);
end component;
--=============================================================================
component quad_decoder 
    port (
      filt_A: in  std_logic;
	  filt_B: in  std_logic;
      Clk:    in  std_logic;
      Rst:    in  std_logic;
      Count:  out std_logic;
      UpDown: out std_logic
    );
end component;
--=============================================================================
component position_counter 
    port(	
        Rst      : in std_logic;
        Clk      : in std_logic;
        Enable   : in std_logic;
        UpDown   : in std_logic;
        Q_count  : out std_logic_vector (width -1 downto 0)
    );
end component;
--=============================================================================
component position_latch 
    port (
        Data: in std_logic_vector (width -1 downto 0);
        Rst : in std_logic; 
        Clk : in std_logic;
        OE  : in std_logic;
        Q 	: inout std_logic_vector (width -1 downto 0)
    );
end component ;
--=============================================================================
begin
U1: Digital_Filter
	port map (ChA=> ChA, ChB=> ChB, Clk=> Clk, Rst=> Rst, ChA_filt=> filt_cha, ChB_filt=> filt_chb);
U2: Quad_decoder 
	port map (filt_A=> filt_cha, filt_B=> filt_chb, Clk=> Clk, Rst=> Rst, Count=> Cnt_en, UpDown=> Up_nDown);
U3: Position_counter 
	port map (Rst=> Rst, Clk=> Clk, Enable=> cnt_en, UpDown=> Up_nDown, Q_count=> t_count);
U4: Position_latch 
    port map (Data=>t_count, Rst=> rst, Clk=> clk, OE=> OE, Q=> Data_out);
--=============================================================================
  	CNT <= cnt_en;
  	up_down <= up_ndown;
	D <= data_out;
end behavior; 

• Выкиньте макс, синтезите квартусом. — SM   (16.08.2004 13:42, пустое)
  • Ok. Замечания пропали. — _гоша   (16.08.2004 20:22, пустое)
• Хмм если мне память не изменяет в максе очень слабая поддержка (+) — des00   (16.08.2004 10:30, 247 байт)
  • Ошибаетесь, очень даже можно создавать иерархии. Проблема в другом. — Aquarius   (16.08.2004 15:22, пустое)
    • Может быть :)) с VHDL у меня рассовая не любовь, за сим на нем не работал — des00   (17.08.2004 06:04, пустое)