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У меня странный результат при одих исходных (проверял несколько раз):
Release 5.2.03i - Map F.31
Xilinx Mapping Report File for Design 'Core'
Design Information
------------------
Command Line : C:\Xilinx_soft\bin\nt\map.exe -quiet -p xc2S30-tq144-5 -cm
speed -detail -gm exact -ignore_keep_hierarchy -pr b -k 4 -c 100 -tx off -o
map.ncd core.ngd core.pcf
Target Device : x2s30
Target Package : tq144
Target Speed : -5
Mapper Version : spartan2 -- $Revision: 1.4 $
Mapped Date : Mon Aug 16 19:01:21 2004
Design Summary
--------------
Number of errors: 0
Number of warnings: 1
Logic Utilization:
Number of Slice Flip Flops: 184 out of 864 21%
Number of 4 input LUTs: 274 out of 864 31%
Logic Distribution:
Number of occupied Slices: 198 out of 432 45%
Number of Slices containing only related logic: 198 out of 198 100%
Number of Slices containing unrelated logic: 0 out of 198 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 290 out of 864 33%
Number used as logic: 274
Number used as a route-thru: 16
Number of bonded IOBs: 51 out of 92 55%
IOB Flip Flops: 45
Number of Tbufs: 256 out of 480 53%
Number of Block RAMs: 2 out of 6 33%
Number of GCLKs: 1 out of 4 25%
Number of GCLKIOBs: 2 out of 4 50%
Number of DLLs: 1 out of 4 25%
Total equivalent gate count for design: 44,516
Additional JTAG gate count for IOBs: 2,544
Peak Memory Usage: 51 MB
Timing errors: 0 Score: 0
Constraints cover 30424 paths, 0 nets, and 2054 connections (92.6% coverage)
Design statistics:
Minimum period: 16.148ns (Maximum frequency: 61.927MHz)
Minimum input arrival time before clock: 11.930ns
Maximum output required time before clock: 24.174ns
Release 6.2.03i Map G.31a
Xilinx Mapping Report File for Design 'Core'
Design Information
------------------
Command Line : C:\Xilinx_soft\ISE6.2\bin\nt\map.exe -p xc2S30-tq144-5 -cm
speed -detail -gm exact -ignore_keep_hierarchy -ol high -timing -pr b -k 4 -c
100 -tx off -o map.ncd core.ngd core.pcf
Target Device : x2s30
Target Package : tq144
Target Speed : -5
Mapper Version : spartan2 -- $Revision: 1.16.8.1 $
Mapped Date : Mon Aug 16 19:06:55 2004
Design Summary
--------------
Number of errors: 0
Number of warnings: 3
Logic Utilization:
Number of Slice Flip Flops: 184 out of 864 21%
Number of 4 input LUTs: 276 out of 864 31%
Logic Distribution:
Number of occupied Slices: 199 out of 432 46%
Number of Slices containing only related logic: 199 out of 199 100%
Number of Slices containing unrelated logic: 0 out of 199 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 307 out of 864 35%
Number used as logic: 276
Number used as a route-thru: 31
Number of bonded IOBs: 51 out of 92 55%
IOB Flip Flops: 45
Number of Tbufs: 256 out of 480 53%
Number of Block RAMs: 2 out of 6 33%
Number of GCLKs: 1 out of 4 25%
Number of GCLKIOBs: 2 out of 4 50%
Number of DLLs: 1 out of 4 25%
Total equivalent gate count for design: 44,528
Additional JTAG gate count for IOBs: 2,544
Peak Memory Usage: 60 MB
Timing errors: 0 Score: 0
Constraints cover 30350 paths, 0 nets, and 2057 connections
Design statistics:
Minimum period: 18.626ns (Maximum frequency: 53.688MHz)
Minimum input required time before clock: 10.907ns
Maximum output delay after clock: 24.541ns
E-mail: 
info@telesys.ru
