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parameters
(
WIDTH=8
);subdesign bidir_reg
(
inout_a[WIDTH-1..0]:bidir;
inout_b[WIDTH-1..0]:bidir;
ena_w_a, ena_w_b:input;
clk_a, clk_b:input;
nreset,direction:input;
)
variable
reg_a[WIDTH-1..0], reg_b[WIDTH-1..0]:dffe;
begin
reg_a[].(CLK, ENA, CLRN)=(clk_a, ena_w_a, nreset);
reg_b[].(CLK, ENA, CLRN)=(clk_b, ena_w_b, nreset);
reg_a[]=inout_a[];
reg_b[]=inout_b[];
for i in 0 to WIDTH-1 generate
inout_a[i] = tri(reg_b[i],direction);
inout_b[i] = tri(reg_a[i],not direction);
end generate;
end;
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