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применять можно с помощью визарда или примерно так (для VHDL):
PLL_U1 : altclklock
GENERIC MAP (
inclock_period => integer(1.0e6/PCI_Freq),
clock0_boost => integer(integer(ADC_Freq)/8),
clock0_divide => integer(integer(PCI_Freq)/8),
clock1_boost => integer(integer(ADC_Freq)/4),
clock1_divide => integer(integer(PCI_Freq)/8),
operation_mode => "NORMAL",
intended_device_family => "APEX20KE",
valid_lock_cycles => 1,
invalid_lock_cycles => 5,
valid_lock_multiplier => 1,
invalid_lock_multiplier => 5,
outclock_phase_shift => 0,
lpm_type => "altclklock"
)
PORT MAP (
inclock => clk_pci,
clock0 => clock0,
clock1 => clock2,
locked => open
);
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