Отправлено =TriD= 17 декабря 2004 г. 12:28 В ответ на: Ответ: отправлено =TriD= 17 декабря 2004 г. 12:23

...
signal rx_counter : std_logic_vector(10 downto 0) := "00000000000";
signal rx_reg : std_logic_vector(7 downto 0);
signal rx_bit_n :INTEGER range 0 to 10 := 0;
signal rx_process : std_logic := '0';
signal rx_dout_complete: std_logic := '0';
...

rx_proc : process(clock, reset)
begin
if reset = '1' then
rx_process <= '0';

elsif rising_edge(clock) then
-- Waits for a Start Bit
if rx_process = '0' then
if rx = '0' then
rx_counter <= CONV_STD_LOGIC_VECTOR((ClockFreq/BoudRate)/2,11); -- samples in the middle of the bit length
rx_process <= '1';
rx_bit_n <= 0;
end if;
rx_dout_complete <= '0';
else
-- timer
if rx_counter = 0 then
rx_counter <= CONV_STD_LOGIC_VECTOR(ClockFreq/BoudRate,11);
case rx_bit_n is
when 0 => -- confirms star bit, else discards the data
if rx = '0' then
rx_bit_n <= rx_bit_n + 1;
else
rx_process <= '0';
end if;

when 1|2|3|4|5|6|7|8 => -- Data bits
rx_reg <= rx & rx_reg(7 downto 1);
rx_bit_n <= rx_bit_n + 1;

when 9 => -- Stop bits
rx_dout_complete <= '1';
rx_process <= '0';
when 10 =>

end case;
else
rx_counter <= rx_counter - 1;
end if;
end if;
end if;
end process rx_proc;