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-- RAM256x9SSR_TB
library IEEE, APA;
use IEEE.std_logic_1164.all;
entity testbench is
end testbench;
architecture default of testbench is
component qqram
port(
DO : out std_logic_vector (7 downto 0);
RCLOCK : in std_logic;
WCLOCK : in std_logic;
DI : in std_logic_vector (7 downto 0);
WRB : in std_logic;
RDB : in std_logic;
WADDR : in std_logic_vector (7 downto 0);
RADDR : in std_logic_vector (7 downto 0);
DOS : out std_logic;
WBLKB : in std_logic;
RBLKB : in std_logic;
DIS : in std_logic);
end component;
signal Clk, RCLKS, WCLKS : std_logic;
signal A, RADDR, WADDR, DO, DI : std_logic_vector(7 downto 0);
signal WRB, RDB, WBLKB, RBLKB, DOS, DIS : std_logic;
begin
RCLKS<=Clk;
WCLKS<=Clk;
RADDR<=A;
WADDR<=A;
process
begin
wait for 50 ns;
clk <= '0';
wait for 50 ns;
clk <= '1';
end process;
process
begin
DIS<='1';
WBLKB<='0';
RBLKB<='0';
RDB<='1';
WRB<='1';
A<=B"00000000";
DI<=B"00000000";
wait for 200 ns;
WRB<='0';
wait for 200 ns;
WRB<='1';
wait for 200 ns;
RDB<='0';
wait for 200 ns;
RDB<='1';
wait for 1000 ns;
end process;
xx : qqram port map(
RCLOCK => RCLKS, WCLOCK => WCLKS,
DO => DO, WADDR => WADDR, RADDR => RADDR, DI => DI,
WRB => WRB, RDB => RDB, WBLKB => WBLKB, RBLKB => RBLKB, DOS => DOS, DIS => DIS);
end default;
------------------------------------------------
-- qqram
library IEEE, APA;
use IEEE.std_logic_1164.all;
entity qqram is
port(
DO : out std_logic_vector (7 downto 0);
RCLOCK : in std_logic;
WCLOCK : in std_logic;
DI : in std_logic_vector (7 downto 0);
WRB : in std_logic;
RDB : in std_logic;
WADDR : in std_logic_vector (7 downto 0);
RADDR : in std_logic_vector (7 downto 0);
DOS : out std_logic;
WBLKB : in std_logic;
RBLKB : in std_logic;
DIS : in std_logic);
end qqram;
architecture STRUCT_ram256x8 of qqram is
component PWR
port(Y : out std_logic);
end component;
component GND
port(Y : out std_logic);
end component;
component RAM256x9SSR
port(
RCLKS : in std_logic;
WCLKS : in std_logic;
DO8 : out std_logic;
DO7 : out std_logic;
DO6 : out std_logic;
DO5 : out std_logic;
DO4 : out std_logic;
DO3 : out std_logic;
DO2 : out std_logic;
DO1 : out std_logic;
DO0 : out std_logic;
DOS : out std_logic;
WPE : out std_logic;
RPE : out std_logic;
WADDR7 : in std_logic;
WADDR6 : in std_logic;
WADDR5 : in std_logic;
WADDR4 : in std_logic;
WADDR3 : in std_logic;
WADDR2 : in std_logic;
WADDR1 : in std_logic;
WADDR0 : in std_logic;
RADDR7 : in std_logic;
RADDR6 : in std_logic;
RADDR5 : in std_logic;
RADDR4 : in std_logic;
RADDR3 : in std_logic;
RADDR2 : in std_logic;
RADDR1 : in std_logic;
RADDR0 : in std_logic;
DI8 : in std_logic;
DI7 : in std_logic;
DI6 : in std_logic;
DI5 : in std_logic;
DI4 : in std_logic;
DI3 : in std_logic;
DI2 : in std_logic;
DI1 : in std_logic;
DI0 : in std_logic;
WRB : in std_logic;
RDB : in std_logic;
WBLKB : in std_logic;
RBLKB : in std_logic;
PARODD : in std_logic;
DIS : in std_logic);
end component;
signal VDD, VSS, n1, n2, n3, n4 : std_logic;
begin
U1 : GND port map(Y => VSS);
M0 : RAM256x9SSR port map(RCLKS => RCLOCK, WCLKS => WCLOCK, DO8 => n1, DO7 => DO(7), DO6 => DO(6),
DO5 => DO(5), DO4 => DO(4), DO3 => DO(3), DO2 => DO(2), DO1 => DO(1),
DO0 => DO(0), DOS => DOS, WPE => n3, RPE => n4, WADDR7 => WADDR(7), WADDR6 => WADDR(6),
WADDR5 => WADDR(5), WADDR4 => WADDR(4), WADDR3 => WADDR(3), WADDR2 => WADDR(2),
WADDR1 => WADDR(1), WADDR0 => WADDR(0), RADDR7 => RADDR(7), RADDR6 => RADDR(6),
RADDR5 => RADDR(5), RADDR4 => RADDR(4), RADDR3 => RADDR(3), RADDR2 => RADDR(2),
RADDR1 => RADDR(1), RADDR0 => RADDR(0), DI8 => VSS, DI7 => DI(7), DI6 => DI(6),
DI5 => DI(5), DI4 => DI(4), DI3 => DI(3), DI2 => DI(2), DI1 => DI(1),
DI0 => DI(0), WRB => WRB, RDB => RDB, WBLKB => WBLKB, RBLKB => RBLKB, PARODD => VSS, DIS => DIS);
end STRUCT_ram256x8;
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