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New Features in the Quartus II Software Version 4.2
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The Quartus® II software version 4.2 includes new features in the following areas:
New Device Support
EDA Tool Support
PowerPlay Power Analyzer
Incremental Synthesis
Integrated Synthesis
In-System Memory Content Editor
SignalTap II Logic Analyzer
LogicLock Design Example
Early Timing Estimate
Platform Migration
Revisions
Chip Editor & Resource Property Editor
SOPC Builder
Logic Options
Primitives & Megafunctions
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New Device Support:
The Quartus II software version 4.2 includes support for several new devices, including members of the following device families:
Configuration Devices:
Cyclone™ II
Stratix® II
HardCopy® II
For information on all devices supported in the Quartus II software version 4.2, go to Devices & Adapters.
Full Device Support:
Full compilation, simulation, timing analysis, and programming support is available for the following new devices and device packages:
Cyclone II Devices:
EP2C5
EP2C8
EP2C20
EP2C35
EP2C50
EP2C70
Stratix II Device Family:
EP2S60ESF484
EP2S60ESF672
EP2S60ESF1020
EP2S30F484
EP2S30F672
EP2S130F1020
EP2S130F1508
Configuration Devices:
EPCS64 (Full Support)
Preliminary Device Support
In the near future, you will be able to migrate Stratix II designs to HardCopy II devices. When compiling a design for a Stratix II device in the Quartus II software version 4.2, the following information about the migration path to the HardCopy II devices is given in the compilation report:
package
logic
pins
memory
PLLs
DLLs
SERDES
configuration
This preliminary support is provided for the following HardCopy II devices:
HardCopy II Devices:
HC210 FBGA-484
HC220 FBGA-672
HC220 FBGA-780
HC230 FBGA-1020
HC240 FBGA-1020
HC240 FBGA-1508
EDA Tool Support:
The Quartus II software version 4.2 supports the following EDA tools (an asterisk * indicates tools that include NativeLink® integration support):
Synthesis Tools:
Mentor Graphics® LeonardoSpectrum™ version 2004b *
Synopsys® Design Compiler version 2004.09
Synopsys Design Compiler FPGA version 2004.12
Synopsys FPGA Compiler II version 3.8 *
Synopsys Precision RTL Synthesis version 2004c *
Synplicity Synplify and Synplify Pro version 8.0 *
Magma Design Automation PALACE version 2.4 *
Verification Tools:
Cadence NC-Verilog version 5.1 s017 *
Cadence NC-VHDL version 5.1 s017 *
Cadence Verilog-XL version 3.3 (PC)
Cadence Verilog-XL version 5.1 s017(UNIX workstations)
Mentor Graphics ModelSim® version 5.8e *
Mentor Graphics ModelSim-Altera® version 5.8e *
Mentor Graphics Tau version SDD 2004
Synopsys PrimeTime version 2004.06 *
Synopsys VCS-MX version 7.1.1 L1 *
Synopsys VSS version 2002.06
Synopsys VCS version 7.1.1 L1
Synopsys Formality 2004.12
Cadence Incisive Conformal version 4.3.5.a
The Quartus II software version 4.2 supports the following new EDA features:
Support for the Synopsys Formality software.
Support for performing formal verification using Quartus II Integrated Synthesis and the Conformal Incisive software.
Power analysis using the Quartus II software and the ModelSim, NC-Verilog, NC-VHDL, and VCS simulation tools.
PowerPlay Power Analyzer:
The PowerPlay Power Analyzer enables you to create high-quality power estimations for designs. The PowerPlay Power Analyzer supports thermal planning and power supply planning efforts by providing thermal power-dissipation and power-consumption estimates for a design, based on input information from a variety of data sources that you provide.
Incremental Synthesis:
Incremental synthesis is part of the Quartus II Compiler flow that allows you to resynthesize isolated portions, or partitions, of the design to which you made design changes. Resynthesizing only specified partitions of the design reduces initial synthesis time, resynthesis time, and run-time memory use. Incremental synthesis also preserves the quality of results of the initial compilation by storing information, such as node name assignments for all registered and combinational nodes. The compilation results for partitions that do not go through synthesis again are in storage and untouched by the Compiler during resynthesis.
Integrated Synthesis:
Analysis & Synthesis includes Quartus II Integrated Synthesis, which fully supports the Verilog HDL and VHDL languages and provides options to control the synthesis process.
In-System Memory Content Editor:
The In-System Memory Content Editor now provides greater control of the selection of data, allowing you to select specific address ranges of data, and to quickly replace your selections with new standard or custom values.
SignalTap II Logic Analyzer:
In the SignalTap® II Logic Analyzer, you can now manipulate objects more easily with the new Arrange all Objects command in the Advanced Trigger Condition Editor window. In the Setup tab, new options in the Lock Mode list prevent the inadvertent loss of data when transferring between the Setup and the Advanced Trigger tabs. In the Waveform View, new features enhance the ability to select waveforms and to invert signals to show polarity.
LogicLock Design Example:
For this release, a new LogicLock™ example is added to the qdesigns/ll_makefile directory when you install the Quartus II software version 4.2. The design contains an example of using LogicLock and a makefile to implement a "bottom-up" design flow. This flow allows you to easily break a large design up into separate Quartus sub-projects, and then merge the results into a top-level project. This division facilitates team-based designs, and when used with a makefile, can greatly reduce development time by selectively recompiling only sub-projects whose source files have changed.
Early Timing Estimate:
You can run an early timing estimate to obtain preliminary timing data without completing fitting.
Platform Migration:
For the Quartus II software version 4.2, you can migrate a design to a different platform, or you can migrate a design from one directory to another on the same platform, and still compile and view results successfully.
Revisions:
The Revisions dialog box (Project menu) has been improved and expanded, allowing you to customize the display and order of revisions. Also, you can use the Compare Revisions dialog box to compare compilation results and assignments from different revisions. You can export compared revisions as Comma-Separated Value Files (.csv) for use outside the Quartus II software.
Chip Editor & Resource Property Editor:
Both the Chip Editor and the Resource Property Editor now fully support Stratix II devices. You can now delete atoms in the Chip Editor, and you can now select multiple resources at once in the Chip Editor, and filter the selection.
SOPC Builder:
The SOPC Builder can now automatically add specialized circuitry to support transactions between peripherals that operate on different clocks. Additionally, the new Component Editor helps integrate logic into SOPC Builder systems.
Logic Options:
The Quartus II software version 4.2 supports the following new logic options:
Always Enable Input Buffers
Enable M512 Memory Blocks
External Pin Connection
Extract Verilog State Machines
Extract VHDL State Machines
Guarantee I/O Paths Have Zero Hold Time at Fast Timing Corner
Passive Resistor
PLL External Feedback Board Delay
Preserve PLL Counter Order
QDR D Pin Group
Show "X" on Timing Violation
Show Setup and Hold Time Violations
Primitives & Megafunctions:
The Quartus II software version 4.2 supports the following new megafunctions:
DFFEAS Primitive
altsquare (Squarer)
altufm_i2c (User Flash Memory with Inter-Integrated Circuit Protocol)
altufm_osc (I/O MAX® II Oscillator)
altlvds_rx (LVDS) (Support for Cyclone and Cyclone II Devices)
altlvds_tx (LVDS) (Support for Cyclone and Cyclone II Devices)
E-mail: 
info@telesys.ru
