Отправлено dxp 09 декабря 2004 г. 14:07 В ответ на: Ответ: отправлено SAZH 09 декабря 2004 г. 13:11

Вот сам вопрос и ответ на него:

Вопрос:

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My synchronous design has several parts. Each part has its own speed requirements - so different clock timings are needed.

1. One way is to create special clock enable signal and supply low-speed parts with this signal (and set multicycle constraints for this parts). For example, clock that is needed for fast logic is 160 MHz and low-speed logic can successfully operates at 40 MHz. So I create 'Enable' signal, that becomes active only every 4th clock cycle, and low-speed logic works only when 'Enable' is active. Then I set multicycle assigments for the low-speed logic and that is all.

This way is correct, workable because all parts operate at the same (single) clock. But this way is some unwieldy. It requires enough handicraft.

2. Another way is to derive two clocks (with different frequencies) from FPGA's PLL. For example, I derive 160 MHz clock and 40 MHz clock. 160 MHz clock for fast logic and 40 MHz clock for low-speed one.

It seems to me correct too, because both clocks have the same source - VCO (in PLL). But I am not sure and so I have some questions.

Now the questions:
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1. Is the second way correct?

2. Can I treat the second low-frequency clock (40 MHz) as divided 160 MHz clock? In other words, is the clock skew (across chip) in case of two clocks from one PLL large than clock skew (across chip) in case of one (single) clock?

3. How large clock skew between these clocks?

4. Are there some yet disadvantages?
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Ответ:

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Hi Harry,

In this case, I would suggest to use the second solution instead - use the PLL function. However, for further information on the functionality of a PLL, please refer to the Quartus II Help or to the ALTPLL Userguide . In this, you will find that the altpll megafunction can reduce clock delay and skew. The advantage in using a megafunction such as the altpll is that is is optimized for the Altera device.

Regards,
Marlon Mendoza 
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А в означенном документе () на странице 53 в разделе "Clock Domain Transfers" сказано буквально следующее:

Synchronous Transfers

If the two clocks for domain transfer come from a single PLL and on the same clock type (both global clocks or both regional clocks), then all synchronous register-to-register transfers (e.g., 50 MHz to 50 MHz, or 50 MHz to 100 MHz) work across all conditions. No special design considerations need to be made.

Вот это как раз наш случай.

Я и сам до сих пор делал, как Вы сказали - через multicycle разруливал. Но этот способ хоть и проверенный и надежный, но довольно громоздок. И если есть специальные средсва, облегчающие задачу, то почему бы не испльзовать? Ведь в самом деле - генератор в ФАПЧ один и тот же, работает на 800 МГц, далее с него получаются делением две частоты. Они синхронны! Весь вопрос только в некотором сдвиге фазы, т.к. делители все-таки разные и пути (слои) для распространения тоже разные. Но и то, и другое должны быть малы... А иначе зачем вообще тогда два клока с одного ФАПЧа, если их использовать вместе нельзя? Да еще и с возможностью программируемого фазового сдвига?!

• http://www.altera.com/literature/ug/ug_altpll.pdf

• Ответ: — SAZH   (09.12.2004 14:57, 544 байт)