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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sine_cos is
port (
clk : in std_logic;
reset : in std_logic;
en : in std_logic;
sine : buffer std_logic_vector(7 downto 0);
cos : buffer std_logic_vector(7 downto 0)); end sine_cos;
architecture behave_sine_cos of sine_cos is
signal sine_r, cos_r : std_logic_vector(7 downto 0);
begin -- behave_sine_cos
sine <= sine_r + (cos_r(7) & cos_r(7) & cos_r(7) & cos_r(7 downto 3));
cos <= cos_r - (sine(7) & sine(7) & sine(7) & sine(7 downto 3));
registers: process (clk, reset)
begin -- process registers
if reset = '0' then -- asynchronous reset (active low)
sine_r <= "00000000";
cos_r <= "01111000";
elsif clk'event and clk = '1' then -- rising clock edge
if (en = '1') then
sine_r <= sine;
cos_r <= cos;
end if;
end if;
end process registers;
end behave_sine_cos;
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