Отправлено net 15 апреля 2005 г. 00:01 В ответ на: IMHO не правильное (+) отправлено SM 14 апреля 2005 г. 08:48

Capacitive Loading
The “AC Operating Conditions” table in each device family data sheet
specifies an output capacitance condition (C1) for parameters relating to
external performance. For most Altera devices, C1 is 35 pF for active
signals and 5 pF for disabling output buffers.
Device packages and board-level trace capacitance contribute the majority
of loading capacitance. The specified 35-pF load condition is a
representative value for most CMOS circuits. For applications in which a
device drives a higher capacitance, performance decreases as the
capacitive load increases.
Device sockets are a source of both capacitive and inductive loading. Once
a system is finalized for production, sockets should be removed if
possible, and the devices should be mounted directly onto the PCB. Direct
board mounting reduces both the capacitive and inductive loads as well
as noise from socket contacts.
Altera Corporation 9
Operating Requirements for Altera Devices Data Sheet
To ensure the highest circuit performance, the capacitance on device
outputs should be minimized. Because wiring traces on the PCB, device
input pins, and device packaging all contribute to the total capacitance,
the following guidelines should be observed:
n Board layout should ensure that signals run perpendicular to each
other to provide a minimum capacitive coupling effect. Also, signal
traces should be kept as short as possible.
n A high-current buffer should be used to speed the signal to all
destinations for networks in which a single source drives many loads.
The lack of VCC and ground planes or excessive trace lengths can cause
problems with radiated coupling of noise into logic signals and with
transmission-line effects on signal quality. These ringing and noise
elements on logic levels can lead to circuit reliability problems. When
recommended layout practices cannot be implemented to prevent
transmission-line problems, a small series resistor (10 W to 30 W) can be
used to reduce the undershoot or overshoot magnitude on signal edges.
This resistor dampens the ringing that can occur on long board traces and
prevents false triggering.

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