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1)New Device Support
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2)EDA Tool Support
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3)Quartus Incremental Compilation
4)Pin Planner
5)State Machine Viewer
6)HardCopy II Designs
7)Parallel Flash Loader
8)Common Flash Interface
9)SignalTap II Logic Analyzer Incremental Compilation
10)New logic options:
Add D and Q Ports of Register Node to Simulation Output Waveforms
Add Pass-Through Logic to Inferred RAMs
Add Signal to Simulation Output Waveforms
Alias
Ignore translate_off and translate_on Synthesis Directives
Maintain Compatibility with All Stratix II M-RAM Versions
Maximum DSP Block Usage
Maximum Number of M-RAM Memory Blocks
Maximum Number of M4K Memory Blocks
Maximum Number of M512 Memory Blocks
Perform Gate-Level Register Retiming
11)New megafunctions and primitives:
altfp_add_sub (Floating Point Adder Subtractor)
altparallel_flash_loader (Parallel Flash Loader)
LUT_INPUT primitive
LUT_OUTPUT primitive
E-mail: info@telesys.ru