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//--------------------------------------------------------------------------------------------------
//
// Title : max_min
// Design : xxxxxxxxxx
// Author : postoroniy_v@mail.ru
//-------------------------------------------------------------------------------------------------
//
// File : max_min.v
// Generated : Wed Jun 1 17:37:19 2005
// From : interface description file
// By : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description :
//
//-------------------------------------------------------------------------------------------------
`timescale 1 ns / 1 ps
//{{ Section below this comment is automatically maintained
// and may be overwritten
//{module {max_min}}
module max_min ( out ,in1 ,in2 ,in3 ,in0 );
input [7:0] in1 ;
wire [7:0] in1 ;
input [7:0] in2 ;
wire [7:0] in2 ;
input [7:0] in3 ;
wire [7:0] in3 ;
input [7:0] in0 ;
wire [7:0] in0 ;
output [7:0] out ;
wire [7:0] out,out1,out2 ;
wire p0,p1,p2;
//}} End of automatically maintained section
// -- Enter your statements here -- //
assign p0 = (in0>in1)?1:0;
assign out1 = (p0)?in0:in1;
assign p1 = (in2>in3)?1:0;
assign out2 = (p1)?in2:in3;
assign p2 = (out1>out2)?1:0;
assign out = (p2)?out1:out2;
endmodule
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