[an error occurred while processing this directive]
|
module four_comp
(
input [7:0] in0, in1, in2, in3,
output wire [7:0] out
);
wire temp0 = (in0 < in1)? in1 : in0 ;
wire temp1 = (in2 < in3)? in3 : in2 ;
assign out = (temp0 < temp1)? temp1 : temp0 ;
endmodule
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