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Вот схема из Xilinx DataBook-94, умножавшая у меня частоту в кристаллах без PLL (28->56, 60->120MHz). Описание автора (Peter Alfke):
Feed CLK into XOR gate. XOR output clocks a flipflop. Q is inverted and feeds its own D (typical toggle design). Inverted Q also feeds second input of the aforementioned XOR. XOR output is double-frequency clock. This circuit is reliable (the pulse must first toggle the flip-flop!) and should survive any over-eager simplification attempts by the synthesizer...
AHDL:
SUBDESIGN double
(
IN_CLK : INPUT;
OUT_CLK : OUTPUT;
)VARIABLE
_EQ001 : NODE;
_LC1_A11 : NODE;
_LC3_A11 : NODE;BEGIN
-- Node name is 'OUT_CLK'
OUT_CLK = _LC3_A11;-- Node name is ':1'
_LC1_A11 = DFFE(!_LC1_A11, _LC3_A11, VCC, VCC, VCC);-- Node name is ':2'
_LC3_A11 = LCELL( _EQ001);
_EQ001 = !IN_CLK & !_LC1_A11
# IN_CLK & _LC1_A11;
END;
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