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Но это либа для симуляции примитивов DFFEA и DFFEAS
module prim_gdff (q, d, clk, ena, clr, pre, ald, adt, sclr, sload );
input d,clk,ena,clr,pre,ald,adt,sclr,sload;
output q;
reg q;
reg clk_pre;
initial q = 1'b0;always@ (clk or clr or pre or ald or adt)
begin
if (clr == 1'b1)
q <= 1'b0;
else if (pre == 1'b1)
q <= 1'b1;
else if (ald == 1'b1)
q <= adt;
else if ((clk == 1'b1) && (clk_pre == 1'b0))
begin
if (ena == 1'b1)
begin
if (sclr == 1'b1)
q <= 1'b0;
else if (sload == 1'b1)
q <= adt;
else
q <= d;
end
end
clk_pre <= clk;
end
endmodule
module dffea (d, clk, ena, clrn, prn, aload, adata,q );
input d,clk,ena,clrn,prn,aload,adata;
output q;
wire q;
tri0 aload;
tri1 prn, clrn, ena;reg stalled_adata;
initial
begin
stalled_adata = adata;
endalways @(adata) begin
#1 stalled_adata = adata;
endprim_gdff inst (q,d,clk,ena,!clrn,!prn,aload,stalled_adata,1'b0,1'b0);
endmodule
module dffeas (d, clk, ena, clrn, prn, aload, asdata, sclr, sload, q );
input d,clk,ena,clrn,prn,aload,asdata,sclr,sload;
output q;
wire q;
tri0 aload;
tri1 prn, clrn, ena;reg stalled_adata;
initial
begin
stalled_adata = asdata;
endalways @(asdata) begin
#1 stalled_adata = asdata;
endprim_gdff inst (q,d,clk,ena,!clrn,!prn,aload,stalled_adata,sclr,sload);
endmodule
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