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Timing constraint: TS_sys_clk = PERIOD TIMEGRP "sys_clk" 8.591 ns HIGH 50%;
1548 items analyzed, 93 timing errors detected. (93 setup errors, 0 hold errors)
Minimum period is 12.989ns.
--------------------------------------------------------------------------------
Slack: -2.199ns (requirement - (data path - clock path skew + uncertainty))
Source: U2/CurrState_Sreg0[1] (FF)
Destination: U4/B7.A (RAM)
Requirement: 4.295ns
Data Path Delay: 6.494ns (Levels of Logic = 2)
Clock Path Skew: 0.000ns
Source Clock: sys_clk_c rising at 0.000ns
Destination Clock: sys_clk_ibuf_iso falling at 4.295ns
Clock Uncertainty: 0.000ns
Data Path: U2/CurrState_Sreg0[1] to U4/B7.A
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X17Y33.XQ Tcko 0.626 U2.CurrState_Sreg0[1]
U2/CurrState_Sreg0[1]
SLICE_X15Y31.F2 net (fanout=32) 0.812 U2.CurrState_Sreg0[1]
SLICE_X15Y31.X Tif5x 0.793 U2.m7_i_2
U2/m7_i_2_x1
U2/m7_i_2
SLICE_X4Y30.F4 net (fanout=20) 1.644 U2.m7_i_2
SLICE_X4Y30.X Tilo 0.529 mem_addr_b[3]
U1/MEM_ADDR_B[3]
RAMB16_X0Y3.ADDRA8 net (fanout=1) 1.786 mem_addr_b[3]
RAMB16_X0Y3.CLKA Tback 0.304 U4/B7
U4/B7.A
------------------------------------------------- ---------------------------
Total 6.494ns (2.252ns logic, 4.242ns route)
(34.7% logic, 65.3% route)
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