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3.2.2 Control register
Bit # Access Description
7 RW EN, I2C core enable bit.
When set to ‘1’, the core is enabled.
When set to ‘0’, the core is disabled.
6 RW IEN, I2C core interrupt enable bit.
When set to ‘1’, interrupt is enabled.
When set to ‘0’, interrupt is disabled.
5:0 RW Reserved
Reset Value: 0x00
The core responds to new commands only when the ‘EN’ bit is set. Pending commands
are finished. Clear the ‘EN’ bit only when no transfer is in progress, i.e. after a STOP
command, or when the command register has the STO bit set. When halted during a
transfer, the core can hang the I2C bus.
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