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Mne tozhe interesno (pravda ne prosto :-), a po rabote).
"instantiation" (ot "instance") - v nashih delah - vkluchenie (podkluchenie) modulya
"array instantiation" - vkluchenie massiva moduley
v standarte verilog-a vrode govoritsa chto takim obrazom mozhno podkluchat' tol'ko elementarnye yacheyki ("and", "or" ...) - kak-to mutno
v sovremennyh simulatorah ot cadence mozhno ispol'zovat' konstrukciyu
module_name instance_name[range] (....);
po smyslu eto
module_name instance_name_0 (....);
module_name instance_name_1 (....);
.....
module_name instance_name_N (....);
no v synteze nelzya
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a ya vychital v cadencovskoi conf-e chto sovremennyi sintez beret
SOBSTVENNO ETO YEDINSTVENNYJ NEDOSTATOK VERILOG-a (vs VHDL) - otsutstvie konstrukcii FOR ... GENERATE
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a original'nyj vopros ya sprashival ran'she (pro synhronizatory)
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vot ya v comp.lang.verilog sprashival, no net otveta...
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Lets assume that the library has FF's with set/reset.
The buses (for example)
reg [15:0] strb,wr,r;
should be connected to 16 FFs: strb[i] - to set, wr[i] - to D, r - to Q for each FF.
So I am looking the best way to make the behaviour description.
Verilog does not allow to use buses in always@(posedge...)
Now I use the structural description (16 instances of module FFSR).
But in case of parametrization
parameter bus_width=15;
reg [bus_width:0] strb,wr,r;
this way will not work.
> For one bit the description looks like this
>
> assign STRB_1=strb[1];
> always @(posedge CLK or posedge RST or posedge STRB_1)
> begin: wr_ctrl
> if(STRB_1)
> begin
> r[1]<=1;
> end
> else if(RST)
> begin
> r[1]<=0;
> end
> else
> begin ;
> r[1]<=wr[1];
> end
> end // block: wr_ctrl
>
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