|
|
TITLE "TRANSMITTER";
SUBDESIGN TRANSMITTER
(
clk, nrst, nwr, data[7..0] : INPUT= VCC;
done, sout : OUTPUT;
)
VARIABLE
fsm : MACHINE WITH STATES (STOP, START, SHIFT);
done_data,
bit[7..0], nclr[7..0], nset[7..0], nwr_ena : NODE;
cnt[2..0] : DFFE;
cnt_ena : NODE;
BEGIN
-- transmitter
cnt[].clk= clk;
cnt[].prn= nrst & cnt_ena;
cnt[].ena= cnt_ena;
cnt[].d= cnt[].q-1;
cnt_ena= (fsm == STOP) !# (fsm == START);
fsm .reset= !nrst;
fsm .clk= clk;
fsm .ena= VCC;
done_data= done # ((fsm == SHIFT) & (cnt[] == 0));
done= DFF (done_data, clk, nwr_ena, nrst);
nwr_ena= nwr # !(fsm == STOP);
CASE fsm IS
WHEN STOP => IF done THEN fsm= STOP; ELSE fsm= START; END IF;
WHEN START => fsm= SHIFT;
WHEN SHIFT => IF cnt[] != 0 THEN fsm= SHIFT; ELSE fsm= STOP; END IF;
END CASE;
sout= (fsm == STOP) # ((fsm == SHIFT) & bit[0]);
FOR i IN 0 TO 7 GENERATE nclr[i]= nwr_ena # data[i]; END GENERATE;
FOR i IN 0 TO 7 GENERATE nset[i]= nwr_ena # !data[i]; END GENERATE;
FOR i IN 0 TO 6 GENERATE bit[i]= DFFE (bit[i+1], clk, nclr[i], nset[i], cnt_ena); END GENERATE;
bit[7]= DFFE (bit[0], clk, nclr[7], nset[7], cnt_ena);
END;
|
|
E-mail: 
info@telesys.ru
