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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity DCM_To_DCM is
port (
Kvarz_Clock : in std_logic;
o_Clock : out std_logic;
o_Clock_180 : out std_logic;
Lock_SrcDCM : out std_logic;
Lock_DCM1 : out std_logic;
Lamp : out std_logic
);
end DCM_To_DCM;
architecture Behavioral of DCM_To_DCM is
component DCM
port ( CLKIN : in STD_ULOGIC;
CLK0 : out STD_ULOGIC;
CLK90 : out STD_ULOGIC;
CLK180 : out STD_ULOGIC;
CLK270 : out STD_ULOGIC;
CLK2X : out STD_ULOGIC;
CLK2X180 : out STD_ULOGIC;
LOCKED : out STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKFX : out STD_ULOGIC;
RST : in STD_ULOGIC);
end component;
signal Kvarz_Clock_Int : std_logic;
--////////////////////////////////////////////////
signal Kvarz_Clock2x_FromDCM : std_logic;
signal Kvarz_Clock2x : std_logic;
signal Locked_SrcDCM : std_logic;
--////////////////////////////////////////////////
signal Clock_FromDCM1 : std_logic;
signal Clock : std_logic;
signal Clock180_FromDCM1 : std_logic;
signal Clock180 : std_logic;
signal Locked_DCM1 : std_logic;
--////////////////////////////////////////////////
begin
--*****************************************************************
CLK_IBUFG: IBUFG
port map(
I => Kvarz_Clock,
O => Kvarz_Clock_Int );
Src_DCM: DCM
port map(
CLKIN => Kvarz_Clock_Int,
CLKFB => Kvarz_Clock2x,
RST => '0',
CLK2X => Kvarz_Clock2x_FromDCM,
CLKFX => open,
CLK2X180 => open,
CLK0 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => Locked_SrcDCM
);
CLK2x_BUFG: BUFG
port map(I => Kvarz_Clock2x_FromDCM, O => Kvarz_Clock2x);
Lock_SrcDCM <= Locked_SrcDCM;
--*****************************************************************
DCM1: DCM
port map(
CLKIN => Kvarz_Clock2x,
CLKFB => Clock,
RST => '0',
CLK2X => open,
CLKFX => open,
CLK2X180 => open,
CLK0 => Clock_FromDCM1,
CLK90 => open,
CLK180 => Clock180_FromDCM1,
CLK270 => open,
LOCKED => Locked_DCM1
);
DCM1_CLK0_BUFG: BUFG
port map(I => Clock_FromDCM1, O => Clock);
DCM1_CLK180_BUFG: BUFG
port map(I => Clock180_FromDCM1, O => Clock180);
Lock_DCM1 <= Locked_DCM1;
o_Clock <= Clock;
o_Clock_180 <= Clock180;
--*****************************************************************
Lamp <= '1';
end Behavioral;
При этом получается Lock_DCM1 блокиреутся и сигнал на выходе непостоянный....
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