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module test(
input clk,
input signed [3:0] in,
output signed [7:0] out);
parameter signed [3:0] coeff0 = 10'b1010; // -6 or 10
//////////
wire signed [3:0] Tmp;
/////////////
reg signed [3:0] temp [1:0];
////////
assign Tmp = temp[0];
assign out = Tmp * coeff0;
////////
always @(posedge clk) temp[0] <= in;
endmodule
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