Отправлено Victor® 24 мая 2006 г. 16:59 В ответ на: Подскажите, плиз, микросхему DDR266 SDRAM с 16-битной шиной данных, с 4-х банковой организацией (+) отправлено <font color=gray>vinogradov aleksei</font> 24 мая 2006 г. 12:07

• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
- Read latency 2, 2.5 (clock)
- Burst length (2, 4, 8)
- Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package

K4H511638B-TC/LB3 - B3(DDR333@CL=2.5)
K4H511638B-TC/LA2 - A2(DDR266@CL=2)
K4H511638B-TC/LB0 - B0(DDR266@CL=2.5)

• Samsung — Victor®   (24.05.2006 17:00 80.95.102.226, пустое)

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