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Только не сам НИОС (ему все равно), а контроллер SDRAM, например тот что идет сразу по умолчанию может работать с 8-64 битами.
The core can access SDRAM subsystems with various data widths (8, 16,
32, or 64 bits), various memory sizes, and multiple chip selects. The
Avalon interface is latency-aware, allowing read transfers to be pipelined. The core can optionally share its address and data buses with other offchip Avalon tristate devices. This feature is valuable in systems that have limited I/O pins, yet must connect to multiple memory chips in addition to SDRAM.
Например с контроллером идут настройки для памяти Single NEC D4564163-A80 chip (64 MByte x 16).
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