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Started : "Compile HDL Simulation Libraries".
XILINX = 'C:\Xilinx'
Library Source => 'C:\Xilinx'
Compilation Mode = FAST
Scheduling library installation & compilation for VIRTEX-II Pro
--> Installing Xilinx smartmodel library .....
> Environment variable LMC_HOME = 'c:\Xilinx\smartmodel\nt\installed_nt'
> Extracting model names from 'C:\Xilinx\smartmodel\nt\image\sl_toc.dat'
> Creating 'model.list' at current directory
Library Image directory : 'C:\Xilinx\smartmodel\nt\image'
Installation directory : 'c:\Xilinx\smartmodel\nt\installed_nt'
Running installer......
child process returns status - Ran or Active
Command Line: C:\Xilinx\smartmodel\nt\image\pcnt\cmd_admin.exe -install C:\Xilinx\smartmodel\nt\image c:\Xilinx\smartmodel\nt\installed_nt -edav qsim -edav cds -edav vss -edav systemc -edav other -platform pcnt model.list
Synopsys/Logic Modeling sl_admin
Copyright (c) 1984-2000 Synopsys Inc. ALL RIGHTS RESERVED
Version: 02042
Reading Library
Reading Media
Checking user selections
Loading models....
Loading model: dcc_fpgacore_swift, version: 02402, platform: pcnt
Loading model: emac_swift, version: 01022, platform: pcnt
Loading model: glogic_adv_swift, version: 01004, platform: pcnt
Loading model: glogic_swift, version: 04001, platform: pcnt
Loading model: gt10_swift, version: 02221, platform: pcnt
Loading model: gt11_swift, version: 01016, platform: pcnt
Loading model: gt_swift, version: 01602, platform: pcnt
Loading model: ppc405_adv_swift, version: 01010, platform: pcnt
Loading model: ppc405_swift, version: 04003, platform: pcnt
Updating Configuration files
Writing: c:\Xilinx\smartmodel\nt\installed_nt/data/pcnt.lmc
Updating Library Versioned links
Updating Documentation files
Updating Library cache
Install complete
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vsim.exe -version
Compiling Xilinx HDL Libraries for ModelSim SE Simulator
Language => verilog
Backing up setup files if any...
Output directory => 'C:\Xilinx\verilog\mti_se'
ERROR:CAEInterfaces - child process returns status - Failed
ERROR:CAEInterfaces - Command Line: echo "START_COMPILE unisim"
--> Compiling verilog unisim library
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vlog.exe -version
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vlib C:\Xilinx\verilog\mti_se\unisims_ver
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vmap UNISIMS_VER C:\Xilinx\verilog\mti_se\unisims_ver
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vlog.exe -source -93 -work C:\Xilinx\verilog\mti_se\unisims_ver C:\Xilinx\verilog\mti_se\unisims_ver\unisims_ver_source.v
> Unisim compiled to C:\Xilinx\verilog\mti_se\unisims_ver
ERROR:CAEInterfaces - child process returns status - Failed
ERROR:CAEInterfaces - Command Line: echo "END_COMPILE:unisim"
> Log file C:\Xilinx\verilog\mti_se\unisims_ver\cxl_unisim.log generated
> Library mapping successful, setup file(s) modelsim.ini updated
compxlib[unisims_ver]: No error(s), no warning(s)
ERROR:CAEInterfaces - child process returns status - Failed
ERROR:CAEInterfaces - Command Line: echo "START_COMPILE simprim"
--> Compiling verilog simprim library
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vlib C:\Xilinx\verilog\mti_se\simprims_ver
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vmap SIMPRIMS_VER C:\Xilinx\verilog\mti_se\simprims_ver
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vlog.exe -source -93 -work C:\Xilinx\verilog\mti_se\simprims_ver C:\Xilinx\verilog\mti_se\simprims_ver\simprims_ver_source.v
> Simprim compiled to C:\Xilinx\verilog\mti_se\simprims_ver
ERROR:CAEInterfaces - child process returns status - Failed
ERROR:CAEInterfaces - Command Line: echo "END_COMPILE:simprim"
> Log file C:\Xilinx\verilog\mti_se\simprims_ver\cxl_simprim.log generated
> Library mapping successful, setup file(s) modelsim.ini updated
compxlib[simprims_ver]: No error(s), no warning(s)
--> Compiling verilog XilinxCoreLib library
ERROR:CAEInterfaces - child process returns status - Failed
ERROR:CAEInterfaces - Command Line: echo "START_COMPILE XilinxCoreLib"
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vlib C:\Xilinx\verilog\mti_se\XilinxCoreLib_ver
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vmap UNISIMS_VER C:\Xilinx\verilog\mti_se\unisims_ver
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vmap XILINXCORELIB_VER C:\Xilinx\verilog\mti_se\XilinxCoreLib_ver
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vlog.exe -source -93 -work C:\Xilinx\verilog\mti_se\XilinxCoreLib_ver C:\Xilinx\verilog\mti_se\XilinxCoreLib_ver\XilinxCoreLib_ver_source.v
> XilinxCoreLib compiled to C:\Xilinx\verilog\mti_se\XilinxCoreLib_ver
ERROR:CAEInterfaces - child process returns status - Failed
ERROR:CAEInterfaces - Command Line: echo "END_COMPILE:XilinxCoreLib"
> Log file C:\Xilinx\verilog\mti_se\XilinxCoreLib_ver\cxl_XilinxCoreLib.log generated
> Library mapping successful, setup file(s) modelsim.ini updated
compxlib[XilinxCoreLib_ver]: No error(s), 5 warning(s)
--> Compiling verilog smartmodel(unisim) library
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vmap UNISIMS_VER C:\Xilinx\verilog\mti_se\unisims_ver
> unable to parse initialization file. Check if the
file modelsim.ini is present in the current directory
with read/write permissions
> SWIFT Interface configuration procedure failed
ERROR:CAEInterfaces - child process returns status - Failed
ERROR:CAEInterfaces - Command Line: echo "START_COMPILE:smartmodel(unisim)"
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vlog.exe -source -93 -work C:\Xilinx\verilog\mti_se\unisims_ver C:\Xilinx\verilog\mti_se\unisims_ver\unisims_ver_SmartWrapper_source.v
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vlog.exe -source -93 -work C:\Xilinx\verilog\mti_se\unisims_ver C:\Xilinx\verilog\mti_se\unisims_ver\unisims_ver_SMART_source.v
> Unisim Smart-Models compiled to C:\Xilinx\verilog\mti_se\unisims_ver
ERROR:CAEInterfaces - child process returns status - Failed
ERROR:CAEInterfaces - Command Line: echo "END_COMPILE:smartmodel(unisim)"
> Log file C:\Xilinx\verilog\mti_se\unisims_ver\cxl_smartmodel.log generated
> Library mapping successful, setup file(s) modelsim.ini updated
compxlib[smartmodel]: No error(s), no warning(s)
--> Compiling verilog smartmodel(simprim) library
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vmap SIMPRIMS_VER C:\Xilinx\verilog\mti_se\simprims_ver
> unable to parse initialization file. Check if the
file modelsim.ini is present in the current directory
with read/write permissions
> SWIFT Interface configuration procedure failed
ERROR:CAEInterfaces - child process returns status - Failed
ERROR:CAEInterfaces - Command Line: echo "START_COMPILE:smartmodel(simprim)"
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vlog.exe -source -93 -work C:\Xilinx\verilog\mti_se\simprims_ver C:\Xilinx\verilog\mti_se\simprims_ver\simprims_ver_SmartWrapper_source.v
child process returns status - Ran or Active
Command Line: c:/modeltech_6.1b/win32\vlog.exe -source -93 -work C:\Xilinx\verilog\mti_se\simprims_ver C:\Xilinx\verilog\mti_se\simprims_ver\simprims_ver_Smart_source.v
> Simprim Smart-Models compiled to C:\Xilinx\verilog\mti_se\simprims_ver
ERROR:CAEInterfaces - child process returns status - Failed
ERROR:CAEInterfaces - Command Line: echo "END_COMPILE:smartmodel(simprim)"
> Log file C:\Xilinx\verilog\mti_se\simprims_ver\cxl_smartmodel.log generated
> Library mapping successful, setup file(s) modelsim.ini updated
compxlib[smartmodel]: No error(s), no warning(s)
Log file (compxlib.log) generated.
Process "Compile HDL Simulation Libraries" completed successfully
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