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process(rstn,clk)
variable var : std_logic
begin
if (rstn = '0') then
str_out0 <= '0';
str_out1 <= '0';
elsif (clk'event and clk = '1') then
if (var = '0' and str_in = '1') then -- detect rising front
str_out0 <= '1';
else
str_out0 <= '0';
end if;
if (var = '1' and str_in = '0') then -- detect falling front
str_out1 <= '1';
else
str_out1 <= '0';
end if;
var:= str_in;
end if;
end process;